Method of sequentially biasing bias lines in memory device for program disturbance reduction and memory device utilizing same

Patent metadata

Field	Value
Publication number	US-11222674-B2
Application number	US-202016740491-A
Country	US
Kind code	B2
Filing date	Jan 13, 2020
Priority date	Dec 9, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.

First claim

What is claimed is:

1. A method of operating a memory device, the memory device comprising a top select cell, a top dummy cell and a string of memory cells, the top select cell having a first terminal coupled to a bit line, a control terminal coupled to a top select line, the top dummy cell having a first terminal coupled to a second terminal of the top select cell, a control terminal coupled to a top dummy word line, the string of memory cells having a first terminal coupled to a second terminal of the top dummy cell, and control terminals coupled to respective word lines, the method comprising:
prior to a program operation, applying a pre-pulse voltage of a same magnitude to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines;
wherein the bit line is coupled to an unselected string during the program operation; and
the word lines include selected word lines and unselected word lines during the program operation.

2. The method of claim 1 , further comprising:
in the program operation, applying a top dummy cell voltage to the top dummy word line while applying a program pulse to a selected word line of the word lines.

3. The method of claim 2 , wherein the pre-pulse voltage is less than the top dummy cell voltage.

4. The method of claim 2 , further comprising:
in the program operation, applying a pass voltage to the unselected word lines of the word lines.

5. The method of claim 4 , wherein the pass voltage is less than a program voltage.

6. The method of claim 2 , further comprising:
in the program operation, applying the low voltage to the bit line and the top select line to unselect the string of memory cells.

7. The method of claim 1 , wherein the low voltage is a ground voltage.

8. The method of claim 1 , wherein the memory device is a 3-dimentional NAND flash memory device.

9. The method of claim 1 , wherein:
the memory device further comprises a bottom dummy word line, a bottom select line, a source line configured to receive a ground voltage, a bottom dummy cell, and a bottom select cell, the bottom dummy cell having a first terminal coupled to the second terminal of the string of memory cells, a control terminal coupled to the bottom dummy word line, and a second terminal, and the bottom select cell having a first terminal coupled to the second terminal of the bottom dummy cell, a control terminal coupled to the bottom select line, and a second terminal coupled to the source line; and
the method further comprises applying the pre-pulse voltage to the bottom dummy word line, the bottom select line and the source line while applying the low voltage to the word lines, and sequentially applying the low voltage to the bottom dummy word line, the bottom select line and the source line while applying the low voltage to the word lines.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Shan
• You Kaikai
• Cui Ying
• Jia Jianquan
• Li Kaiwei
• Zhang An

Classifications

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title