Texture memory storage

Patent metadata

Field	Value
Publication number	US-11222396-B2
Application number	US-202117195486-A
Country	US
Kind code	B2
Filing date	Mar 8, 2021
Priority date	Nov 2, 2018
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

In one embodiment, an apparatus, coupled to a computing system, may include a first-level of data bus comprising first-level data lines. The apparatus may include second-level data buses each including second-level data lines. Each second-level data bus may be coupled to a memory unit. The second-level data lines of each second-level data bus may correspond to a subset of the first-level data lines. The apparatus may include third-level data buses each including third-level data lines. Each third-level data bus may be coupled to a sub-level memory unit. The third-level data lines of each third-level data bus may correspond to a subset of the second-level data lines of a second-level data bus along a structural hierarchy. The apparatus may be configured to allow the computing system to load a data block from the first-level data lines to sub-level memory units through the third-level data buses excluding multiplexing operations.

First claim

What is claimed is:

1. An apparatus, coupled to a computing system, the apparatus comprising:
a first-level of data bus comprising a plurality of first-level data lines;
a plurality of second-level data buses each comprising a plurality of second-level data lines, wherein each second-level data bus is coupled to a memory unit, and wherein the plurality of second-level data lines of each second-level data bus corresponds to a subset of the plurality of first-level data lines; and
a plurality of third-level data buses each comprising a plurality of third-level data lines, wherein each third-level data bus is coupled to a sub-level memory unit, and wherein the plurality of third-level data lines of each third-level data bus corresponds to a subset of the plurality of second-level data lines of a second-level data bus along a structural hierarchy,
wherein the apparatus is configured to allow the computing system to load a data block from the plurality of first-level data lines to a plurality of sub-level memory units through the plurality of third-level data buses excluding multiplexing operations.

2. The apparatus of claim 1 , wherein the data block is associated with a plurality of texels and is retrieved from a memory block, and wherein the plurality of texels is stored in the memory block in a texel order that maps the plurality of texels to respective third-level data buses such that each subset of the plurality of texels that have the same associated low order address bits are read onto the same third-level data bus.

3. The apparatus of claim 2 , wherein the texel order is determined based on a two-dimensional array used to organize the plurality of texels before the plurality of texels is stored in the memory block, and wherein each of the plurality of texels is associated with a low order address bit of a first address associated with a position of that texel in the two-dimensional array.

4. The apparatus of claim 2 , wherein the texel order of the plurality of texels in the memory block is determined based on one or more mapping rules, and wherein the one or more mapping rules map the plurality of texels from a two-dimension array into a one-dimensional array in the texel order.

5. The apparatus of claim 4 , wherein the one or more mapping rules map the plurality of texels from the two-dimensional array into the one-dimensional array using a swizzle pattern.

6. The apparatus of claim 4 , wherein the one or more mapping rules map the plurality of texels from the two-dimensional array into the one-dimensional array using an interleaved swizzle pattern.

7. The apparatus of claim 2 , wherein the texel order of the plurality texels stored in the memory block maps the plurality of texels to respective third-level data buses using a mapping relationship applicable to a plurality of texel sizes comprising at least an 8-bit texel size, a 16-bit texel size, or a 32-bit texel size.

8. The apparatus of claim 1 , wherein each third-level data bus is associated with a sub-level memory unit of the plurality of sub-level memory units, and wherein each sub-level memory unit is associated with the same low order address bits.

9. The apparatus of claim 1 , wherein the structural hierarchy causes each bit of the data block to be directly loaded into a corresponding sub-level memory unit excluding multiplexing operations.

10. The apparatus of claim 1 , wherein each memory unit comprises a subset of sub-level memory units of the plurality of sub-level memory units.

11. One or more computer-readable non-transitory storage media, associated with a computing system coupled to an apparatus, embodying software that is operable when executed to:
load a data block onto a first-level of data bus comprising a plurality of first-level data lines;
transmit, by the first level data bus of the apparatus, the data block to a plurality of second-level data buses each comprising a plurality of second-level data lines, wherein each second-level data bus is coupled to a memory unit, and wherein the plurality of second-level data lines of each second-level data bus corresponds to a subset of the plurality of first-level data lines; and
transmit, by each second level data bus of the apparatus, a portion of the data block onto a plurality of third-level data buses each comprising a plurality of third-level data lines, wherein each third-level data bus is coupled to a sub-level memory unit, and wherein the plurality of third-level data lines of each third-level data bus corresponds to a subset of the plurality of second-level data lines of a second-level data bus along a structural hierarchy,
wherein the apparatus is configured to allow the computing system to load the data block from the plurality of first-level data lines to a plurality of sub-level memory units through the plurality of third-level data buses excluding multiplexing operations.

12. The media of claim 11 , wherein the data block is associated with a plurality of texels and is retrieved from a memory block, and wherein the plurality of texels is stored in the memory block in a texel order that maps the plurality of texels to respective third-level data buses such that each subset of the plurality of texels that have the same associated low order address bits are read onto the same third-level data bus.

13. The media of claim 12 , wherein the texel order is determined based on a two-dimensional array used to organize the plurality of texels before the plurality of texels is stored in the memory block, and wherein each of the plurality of texels is associated with a low order address bit of a first address associated with a position of that texel in the two-dimensional array.

14. The media of claim 12 , wherein the texel order of the plurality of texels in the memory block is determined based on one or more mapping rules, and wherein the one or more mapping rules map the plurality of texels from a two-dimension array into a one-dimensional array in the texel order.

15. The media of claim 14 , wherein the one or more mapping rules map the plurality of texels from the two-dimensional array into the one-dimensional array using a swizzle pattern.

16. A method comprising, by a computing system coupled to an apparatus:
loading a data block onto a first-level of data bus comprising a plurality of first-level data lines;
transmitting, by the first level data bus of the apparatus, the data block to a plurality of second-level data buses each comprising a plurality of second-level data lines, wherein each second-level data bus is coupled to a memory unit, and wherein the plurality of second-level data lines of each second-level data bus corresponds to a subset of the plurality of first-level data lines; and
transmitting, by each second level data bus of the apparatus, a portion of the data block onto a plurality of third-level data buses each comprising a plurality of third-level data lines, wherein each third-level data bus is coupled to a sub-level memory unit, and wherein the plurality of third-level data lines of each third-level data bus corresponds to a subset of the plurality of second-level data lines of a second-level data bus along a structural hierarchy,
wherein the apparatus is configured to allow the computing system to load the data block from the plurality of first-level data lines to a plurality of sub-level memory units through the plurality of third-level data buses excluding multiplexing operations.

17. The method of claim 16 , wherein the data block is associated with a plurality of texels and is retrieved from a memory block, and wherein the

Assignees

• Facebook Tech Llc

Inventors

• Seiler Larry

Classifications

• G06T11/10

  Texturing; Colouring; Generation of textures or colours (retouching, inpainting or scratch removal G06T5/77) · CPC title

• G06T15/04

  Texture mapping · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title