Apparatus and method for high-speed ethernet over star quad media

Patent metadata

Field	Value
Publication number	US-11218342-B2
Application number	US-202016935051-A
Country	US
Kind code	B2
Filing date	Jul 21, 2020
Priority date	Oct 25, 2018
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

An Ethernet link is disclosed. The link includes a first Ethernet transceiver and a second Ethernet transceiver configured as a link partner to the first Ethernet transceiver. A shielded twisted quad (STQ) cable is interposed between the first Ethernet transceiver and the second Ethernet transceiver. The STQ cable includes four conductors, each conductor having a first end interfaced with a corresponding input/output (I/O) circuit of the first Ethernet transceiver in a single-ended configuration, and a second end interfaced with a corresponding input/output (I/O) circuit of the second Ethernet transceiver in a single-ended configuration.

First claim

I claim:

1. An Ethernet transceiver circuit, comprising:
four transmit/receive input/output (I/O) circuits configured as differential transceivers to transmit and receive data over a wired coupling in accordance with an Ethernet protocol;
a signaling interface configured to communicatively couple the four transmit/receive I/O circuits to four corresponding shielded twisted quad (STQ) conductors in a single-ended configuration to form four Ethernet signaling channels over the wired coupling.

2. The Ethernet transceiver circuit of claim 1 , wherein:
ones of the differential transceivers are configured with respective positive signal pins to transmit and receive positive components of differential data signals and complement signal pins to transmit and receive complement components of differential data signals; and
the signaling interface is configured to transfer the positive components of the differential data signals to and from the four transmit/receive I/O circuits as single-ended data signals to and from the four STQ conductors.

3. The Ethernet transceiver of claim 2 , wherein the signaling interface further comprises:
differential-to-single-ended converter circuitry that is configured to convert differential transmit data transmitted from ones of the four differential transceivers to single-ended transmit data for transmission over corresponding ones of the four STQ conductors.

4. The Ethernet transceiver of claim 3 , wherein the differential-to-single-ended converter circuitry comprises:
transformer circuitry configured for coupling to ones of the four differential transceivers, the transformer circuitry including
primary coil circuitry having a first terminal coupled to the positive signal pin of a corresponding differential transceiver, the primary coil circuitry having a second terminal coupled to the complement signal pin of the corresponding differential transceiver, the primary coil circuitry to convert the differential data signal to an electromagnetic signal; and
secondary coil circuitry including a secondary coil winding disposed in electromagnetic communication with the primary coil circuitry to receive the electromagnetic signal and to convert the electromagnetic signal to a single-ended data signal.

5. The Ethernet transceiver of claim 4 , wherein:
the secondary coil winding includes a third terminal coupled to a corresponding one of the four STQ conductors, and a fourth terminal terminated to a reference, the reference configured as a ground connection to provide an electrostatic-discharge (ESD) path.

6. The Ethernet transceiver of claim 4 , wherein the secondary coil circuitry further comprises:
a choke circuit to filter high-frequency interference from the data signals, the choke circuit including a first inductor branch coupled to a corresponding one of the four STQ conductors, and a second inductor branch terminated to a reference, the reference configured as a ground connection to provide an electrostatic-discharge (ESD) path; and
wherein the secondary coil winding includes a third terminal coupled to the first inductor branch of the choke circuit and a fourth terminal coupled to the second inductor branch of the choke circuit.

7. The Ethernet transceiver of claim 1 , wherein:
the four transmit/receive I/O circuits are configured to transmit and receive data associated with operating a motor vehicle, an aircraft, or a boat.

8. An Ethernet link, comprising:
a first Ethernet transceiver including a first group of four transmit/receive input/output (I/O) circuits configured as a first group of differential transceivers to transmit first data and receive second data over a first wired coupling in accordance with an Ethernet protocol;
a second Ethernet transceiver configured as a link partner to the first Ethernet transceiver, the second transceiver including a second group of four transmit/receive input/output (I/O) circuits configured as a second group of differential transceivers to receive the first data and transmit the second data over a second wired coupling in accordance with the Ethernet protocol; and
four corresponding shielded twisted quad (STQ) conductors in a single wired coupling interfaced in a first single-ended configuration with the first group of four transmit/receive I/O circuits with first interface circuitry and interfaced in a second single-ended configuration with the second group of four transmit/receive I/O circuits with second interface circuitry to form four Ethernet signaling channels over the single wired coupling.

9. The Ethernet link of claim 8 , wherein:
ones of the first group of differential transceivers are configured with respective positive signal pins to transmit and receive positive components of differential data signals and complement signal pins to transmit and receive complement components of differential data signals; and
the first interface circuitry and the second interface circuitry are configured to transfer the positive components of the differential data signals as single-ended data signals to and from the corresponding first group of four transmit/receive I/O circuits and the corresponding second group of four transmit/receive I/O circuits via the four STQ conductors.

10. The Ethernet link of claim 9 , wherein each of the first interface circuitry and the second interface circuitry further comprises:
differential-to-single-ended converter circuitry that is configured to convert differential transmit data to single-ended transmit data for transmission over the four STQ conductors.

11. The Ethernet link of claim 10 , wherein the differential-to-single-ended converter circuitry for each of the first interface circuitry and the second interface circuitry comprises:
transformer circuitry configured for coupling to ones of the four differential transceivers of the corresponding first interface circuitry or the second interface circuitry, the transformer circuitry including
primary coil circuitry having a first terminal coupled to the positive signal pin of a corresponding differential transceiver, the primary coil circuitry having a second terminal coupled to the complement signal pin of the corresponding differential transceiver, the primary coil circuitry to convert the differential data signal to an electromagnetic signal; and
secondary coil circuitry including a secondary coil winding disposed in electromagnetic communication with the primary coil circuitry to receive the electromagnetic signal and to convert the electromagnetic signal to a single-ended data signal.

12. The Ethernet link of claim 11 , wherein:
the secondary coil winding includes a third terminal coupled to a corresponding one of the four STQ conductors, and a fourth terminal terminated to a reference, the reference configured as a ground connection to provide an electrostatic-discharge (ESD) path.

13. The Ethernet link of claim 11 , wherein the secondary coil circuitry further comprises:
a choke circuit to filter high-frequency interference from the data signals, the choke circuit including a first inductor branch coupled to a corresponding one of the four STQ conductors, and a second inductor branch terminated to a reference, the reference configured as a ground connection to provide an electrostatic-discharge (ESD) path; and
wherein the secondary coil winding includes a third terminal coupled to the first inductor branch of the choke circuit and a fourth terminal coupled to the second inductor branch of the choke circuit.

14. The Ethernet link of claim 8 , wherein:
the four transmit/receive I/O circuits for each of the first Ethernet transceiver and the second Ethernet t

Assignees

• Marvell Asia Pte Ltd

Inventors

• Langner Paul

Classifications

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L12/40013

  Details regarding a bus controller · CPC title

• H01B11/005

  Quad constructions · CPC title

• H04L2012/40273

  the transportation system being a vehicle · CPC title

• H04L12/10

  Current supply arrangements · CPC title