Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter

Patent metadata

Field	Value
Publication number	US-11218155-B2
Application number	US-202017101665-A
Country	US
Kind code	B2
Filing date	Nov 23, 2020
Priority date	Feb 28, 2020
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

First claim

What is claimed is:

1. A digital fractional phase locked loop comprising:
a current mode low pass filter including a DC path, a proportional path and an integral path, each of the proportional path and the integral path including a plurality of transistors configured in a current mirror arrangement and a plurality of switchable arrays tied to certain of the plurality of transistors to functionally implement multipliers and adders, the current mode low pass filter configured to
receive a directional signal based on a comparison of a reference clock and a feedback clock; and
output a control signal based on at least the directional signal when a current steering switch directly controlled by the directional pulse switches to a controlled oscillator; and

the controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on the control signal, the feedback clock being based on the output clock,
wherein the reference clock being aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

2. The digital fractional phase locked loop of claim 1 , wherein the current steering switch is implemented in the proportional path.

3. The digital fractional phase locked loop of claim 1 , wherein the current steering switch switches between a dummy load and the controlled oscillator.

4. The digital fractional phase locked loop of claim 1 , wherein the DC path is configured to center a frequency range for the digital fractional phase locked loop.

5. The digital fractional phase locked loop of claim 1 , wherein an output of the proportional path is connected to the current steering switch.

6. The digital fractional phase locked loop of claim 1 , further comprising
a divider connected to the controlled oscillator; and
a sigma-delta modulator connected to the divider,
wherein the divider and sigma-delta modulator collectively generate the feedback clock.

7. The digital fractional phase locked loop of claim 1 , wherein each switchable array is configured to add or remove a unit current path to adjust a current mirror ratio.

8. The digital fractional phase locked loop of claim 1 , wherein the current mirror arrangement for the integral path and the current mirror arrangement for the proportional path are cascaded current mirror arrangements.

9. A digital filter comprising:
a DC circuit configured to center a frequency range;
an integral circuit;
a proportional circuit, each of the proportional circuit and the integral circuit comprises
a plurality of transistors configured in a current mirror arrangement; and
a plurality of switchable arrays tied to certain of the plurality of transistors to functionally implement multipliers and adders; and

a current steering switch connected to the proportional circuit, the current steering switch switching between a dummy load and a load,
wherein a control signal is output based on a state of the current steering switch.

10. The digital filter of claim 9 , wherein each switchable array is configured to add or remove a unit current path to adjust a current mirror ratio.

11. The digital filter of claim 9 , wherein the DC path includes a plurality of transistors configured in a current mirror arrangement and a plurality of switchable arrays tied to certain of the plurality of transistors to functionally implement multipliers and adders.

12. The digital filter of claim 9 , wherein the current mirror arrangement for the integral circuit and the current mirror arrangement for the proportional circuit are cascaded current mirror arrangements.

13. The digital filter of claim 9 , wherein the control signal is output when the current steering switch is connected to the load.

14. A method, the method comprising:
connecting a plurality of transistors in a current mirror arrangement and connecting a plurality of switchable arrays to certain of the plurality of transistors to functionally implement multipliers and adders in a DC path;
connecting a plurality of transistors in a current mirror arrangement and connecting a plurality of switchable arrays to certain of the plurality of transistors to functionally implement multipliers and adders in an integral path; and
connecting a plurality of transistors in a current mirror arrangement and connecting a plurality of switchable arrays to certain of the plurality of transistors to functionally implement multipliers and adders in a proportional path,
wherein a control signal is output based on a state of a current steering switch.

15. The method of claim 14 , further comprising connecting the current steering switch to the proportional path, the current steering switch configured to switch states between a dummy load and a load.

16. The method of claim 14 , wherein each switchable array is configured to add or remove a unit current path to adjust a current mirror ratio.

17. The method of claim 14 , wherein the current mirror arrangement for the integral path and the current mirror arrangement for the proportional path are cascaded current mirror arrangements.

Assignees

• Ciena Corp

Inventors

• Wen Tingjun
• Aouini Sadok
• Ben-Hamida Naim
• Parvizi Mahdi
• Mikkelsen Matthew

Classifications

• H03L7/1974 Primary

  for fractional frequency division · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L1/00

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title