Managing stray light absorption in integrated photonics devices

Patent metadata

Field	Value
Publication number	US-11217713-B2
Application number	US-202016741988-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Dec 2, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

Fabricating a photonic integrated circuit includes fabricating structures in one or more silicon layers. At least a first silicon layer comprises: one or more photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and one or more light absorbing structures, where at least some of the light absorbing structures include doped silicon. Fabricating the photonic integrated circuit also includes fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

First claim

What is claimed is:

1. An article of manufacture, comprising:
a photonic integrated circuit that includes one or more silicon layers, where at least a first silicon layer comprises:
a plurality of photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and
a plurality of light absorbing structures, where the light absorbing structures include a first set of light absorbing structures each consisting essentially of a doped silicon structure and a second set of light absorbing structures each consisting essentially of a doped or undoped silicon structure at least partially covered with germanium; and

at least a first waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

2. The article of manufacture of claim 1 , further comprising:
at least a first input port in the photonic integrated circuit for receiving first light into the first waveguide, the first light characterized by a first intensity; and
at least a second input port in the photonic integrated circuit for receiving second light into a waveguide in one of the silicon layers, the second light characterized by a second intensity lower than the first intensity;
wherein at least a first photodetector of the one or more photodetectors is positioned at a location in the photonic integrated circuit that: (1) receives a portion of the second light from a first waveguide coupled to the first photodetector, and (2) receives a portion of the first light scattered into the first photodetector from a portion of the photonic integrated circuit other than the first waveguide.

3. The article of manufacture of claim 1 , where the first silicon layer comprises a layer of silicon in a silicon-on-insulator structure that includes a layer of silicon dioxide adjacent to the layer of silicon.

4. The article of manufacture of claim 1 , where the doped silicon of one or more of the light absorbing structures in the first set is characterized by a dopant concentration of greater than 10 18 atoms per cubic centimeter.

5. The article of manufacture of claim 1 , where the quantity of light absorbing structures in the first set is greater than the quantity of light absorbing structures in the second set.

6. The article of manufacture of claim 5 , where at least one of the photodetectors in the first silicon layer is closer to a plurality of the light absorbing structures in the first set than to any of the light absorbing structures in the second set.

7. The article of manufacture of claim 1 , where at least one photodetector comprises a photodiode formed at least in part from germanium covering a portion of the doped silicon of the first silicon layer.

8. The article of manufacture of claim 1 , where the light absorbing structures include a plurality of doped silicon structures that each has a cross-sectional shape that is approximately a polygon, in a cross-sectional plane within the first silicon layer.

9. The article of manufacture of claim 8 , where the plurality of doped silicon structures are each in proximity to neighboring doped silicon structures that together form a tiled pattern in the cross-sectional plane.

10. The article of manufacture of claim 9 , where the plurality of doped silicon structures are each separated from neighboring doped silicon structures in the cross-sectional plane by silicon dioxide.

11. A method for fabricating a photonic integrated circuit, the method comprising:
fabricating structures in one or more silicon layers, where at least a first silicon layer comprises:
a plurality of photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and
a plurality of light absorbing structures, where the light absorbing structures include a first set of light absorbing structures each consisting essentially of a doped silicon structure and a second set of light absorbing structures each consisting essentially of a doped or undoped silicon structure at least partially covered with germanium; and

fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

12. The method of claim 11 , further comprising fabricating in the photonic integrated circuit:
at least a first input port for receiving first light into the first waveguide, the first light characterized by a first intensity; and
at least a second input port for receiving second light into a waveguide in one of the silicon layers, the second light characterized by a second intensity lower than the first intensity;
wherein at least a first photodetector of the one or more photodetectors is positioned at a location in the photonic integrated circuit that: (1) receives a portion of the second light from a first waveguide coupled to the first photodetector, and (2) receives a portion of the first light scattered into the first photodetector from a portion of the photonic integrated circuit other than the first waveguide.

13. The method of claim 11 , where the first silicon layer comprises a layer of silicon in a silicon-on-insulator structure that includes a layer of silicon dioxide adjacent to the layer of silicon.

14. The method of claim 11 , where the doped silicon of one or more of the light absorbing structures in the first set is characterized by a dopant concentration of greater than 10 18 atoms per cubic centimeter.

15. The method of claim 11 , where the quantity of light absorbing structures in the first set is greater than the quantity of light absorbing structures in the second set.

16. The method of claim 15 , where at least one of the photodetectors in the first silicon layer is closer to a plurality of the light absorbing structures in the first set than to any of the light absorbing structures in the second set.

17. The method of claim 11 , where at least one photodetector comprises a photodiode formed at least in part from germanium covering a portion of the doped silicon of the first silicon layer.

18. The method of claim 11 , where the light absorbing structures include a plurality of doped silicon structures that each:
has a cross-sectional shape that is approximately a polygon, in a cross-sectional plane within the first silicon layer,
is in proximity to neighboring doped silicon structures that together form a tiled pattern in the cross-sectional plane, and
is separated from neighboring doped silicon structures in the cross-sectional plane by silicon dioxide.

Assignees

• Ciena Corp

Inventors

• Pelletier François
• O'Keefe Sean Sebastian
• Latrasse Christine
• Painchaud Yves

Classifications

• H10F39/107

  having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays · CPC title

• H10F77/413 Primary

  directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• G02B2006/12126

  Light absorber · CPC title

• G02B6/122

  Basic optical elements, e.g. light-guiding paths · CPC title