Display panel, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11217642-B2
Application number	US-201916472349-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Dec 18, 2018
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A display panel and a method of manufacturing the display panel are provided. The display panel includes an array substrate, a planarization layer, a pixel defining layer, an organic light emitting device, and an inorganic layer disposed between the planarization layer and the pixel defining layer to block moisture and oxygen. An encapsulation structure of the array substrate is cooperatively formed by a combination of a first interlayer dielectric layer contained in a thin-film transistor, the planarization layer, and the inorganic layer.

First claim

What is claimed is:

1. A display panel, comprising:
a display area and a bending area disposed at a side of the display area;
an array substrate comprising a substrate and a thin-film transistor disposed on the substrate, wherein the thin-film transistor comprises an active layer disposed on the array substrate, a first gate insulating layer disposed on the active layer, a first metal layer disposed on the first gate insulating layer, a second gate insulating layer disposed on the first metal layer, a second metal layer disposed the second gate insulating layer, a first interlayer dielectric layer disposed on the second metal layer; and a source metal and a drain metal disposed on the first interlayer dielectric layer;
a planarization layer disposed on the array substrate;
a pixel defining layer disposed above the planarization layer, wherein the pixel defining layer comprises a plurality of pixel defining elements spaced apart from each other;
an organic light emitting device disposed between adjacent pixel defining elements and comprising an anode metal, a light emitting layer, and a cathode layer, wherein the anode metal is electrically connected to the drain metal through a first via hole; and
an inorganic layer disposed between the planarization layer and the pixel defining layer and configured to block moisture and oxygen;
wherein an encapsulation structure for a bottom of the organic light emitting device is cooperatively formed by a combination of the first interlayer dielectric layer contained in the thin-film transistor, the planarization layer, and the inorganic layer;
wherein the thin-film transistor and the organic light emitting device are disposed in the display area, and an organic filling layer is disposed in the bending area and extends through the first gate insulating layer, the second gate insulating layer, and the first interlayer dielectric layer.

2. The display panel of claim 1 , wherein the first via hole extends through the inorganic layer and the planarization layer.

3. The display panel of claim 2 , wherein the first interlayer dielectric layer is an inorganic layer, and the planarization layer is an organic layer.

4. The display panel of claim 1 , wherein the display panel further comprises a second interlayer dielectric layer disposed between the planarization layer and the first interlayer dielectric layer, and wherein the second interlayer dielectric layer is connected to the organic filling layer, and the second interlayer dielectric layer and the organic filling layer are made of a same material.

5. The display panel of claim 4 , wherein the display panel further comprises a stress buffer unit disposed in the display area, and wherein the stress buffer unit sequentially extends through the first gate insulating layer, the second gate insulating layer, and the first interlayer dielectric layer, and is connected to the second interlayer dielectric layer.

6. The display panel of claim 1 , wherein the first metal layer comprises a first gate metal, and the second metal layer comprises a second gate metal.

7. The display panel of claim 1 , further comprising a buffer layer disposed between the substrate and the thin-film transistor.

8. A display device, comprising a display panel and a polarizer, wherein the display panel comprises:
a display area and a bending area disposed at a side of the display area;
an array substrate comprising a substrate and a thin-film transistor disposed on the substrate, wherein the thin-film transistor comprises an active layer disposed on the array substrate, a first gate insulating layer disposed on the active layer, a first metal layer disposed on the first gate insulating layer, a second gate insulating layer disposed on the first metal layer, a second metal layer disposed the second gate insulating layer, a first interlayer dielectric layer disposed on the second metal layer; and a source metal and a drain metal disposed on the first interlayer dielectric layer;
a planarization layer disposed on the array substrate;
a pixel defining layer disposed above the planarization layer, wherein the pixel defining layer comprises a plurality of pixel defining elements spaced apart from each other;
an organic light emitting device disposed between adjacent pixel defining elements and comprising an anode metal, a light emitting layer, and a cathode layer, wherein the anode metal is connected to the drain metal over the first via hole; and
an inorganic layer disposed between the planarization layer and the pixel defining layer and configured to block moisture and oxygen;
wherein an encapsulation structure is formed by a combination of the first interlayer dielectric layer contained in the thin-film transistor, the planarization layer, and the inorganic layer cooperatively format a bottom of the organic light emitting device;
wherein the thin-film transistor and the organic light emitting device are disposed in the display area, and an organic filling layer is disposed in the bending area and extends through the first gate insulating layer, the second gate insulating layer, and the first interlayer dielectric layer.

9. The display device of claim 8 , wherein the first via hole extends through the inorganic layer and the planarization layer.

10. The display device of claim 9 , wherein the first interlayer dielectric layer is an inorganic layer, and the planarization layer is an organic layer.

11. The display device of claim 8 , wherein the display panel further comprises a second interlayer dielectric layer disposed between the planarization layer and the first interlayer dielectric layer, and wherein the second interlayer dielectric layer is connected to the organic filling layer, and the second interlayer dielectric layer and the organic filling layer are made of a same material.

12. The display device of claim 11 , wherein the display panel further comprises a stress buffer unit disposed in the display area, and wherein the stress buffer unit sequentially extends through the first gate insulating layer, the second gate insulating layer, and the first interlayer dielectric layer, and is connected to the second interlayer dielectric layer.

13. The display device of claim 8 , wherein the first metal layer comprises a first gate metal, and the second metal layer comprises a second gate metal.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Wang Ao

Classifications

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H01L51/5259

  Electricity · mapped topic

• H01L27/3246 Primary

  Electricity · mapped topic

• H01L51/56

  Electricity · mapped topic