Array substrate and manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-11217608-B2
Application number	US-202016763331-A
Country	US
Kind code	B2
Filing date	Mar 26, 2020
Priority date	Dec 2, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

The present invention provides an array substrate and a display panel. A second data line is disposed on the array substrate, so that a first data line is connected to the second data line. Therefore, after the first data line is disconnected, signals can be transmitted from the second data line, which solves a technical problem that current display panels cannot solve poor display caused by disconnection of the data lines.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate; and
a source/drain layer disposed at one side of the substrate, wherein the source/drain layer is etched to form a first data line; and
wherein the array substrate comprises a second data line, and a distance between connecting holes of the first data line and the second data line is at least same as a length of one sub-pixel, wherein the array substrate comprises a first metal layer, a second metal layer, and an interlayer insulating layer; the interlayer insulating layer is disposed between the second metal layer and the source/drain layer, the second metal layer is etched to form a second electrode plate of a capacitor and the second data line, a first through-hole is formed on the interlayer insulating layer, and the second data line is connected to the first data line through the first through-hole, wherein the array substrate comprises an active layer, the source/drain layer is etched to form compensation signal lines, a direction of the compensation signal lines is same as a direction of the first data line, and the compensation signal lines are connected to the active layer through the connecting hole, wherein the interlayer insulating layer comprises a second through-hole, the source/drain layer is etched to form power voltage lines, and adjacent columns of the power voltage lines are respectively connected to opposite sides of the second electrode plate through the second through-hole, wherein the first metal layer is etched to form scanning lines, a first electrode plate of the capacitor, and other compensation signal lines, and a direction of the scanning lines is same as a direction of the other compensation signal lines.

2. The array substrate as claimed in claim 1 , wherein a distance of adjacent connecting holes between the first data line and the second data line is same as twice of a sum of a length of the sub-pixel and a distance between adjacent sub-pixels.

3. The array substrate as claimed in in claim 1 , wherein a distance of adjacent connecting holes between the first data line and the second data line is same as a sum of a length of the sub-pixel and a distance between adjacent sub-pixels.

4. The array substrate as claimed in claim 1 , wherein a projection of the first data line on the substrate overlaps a projection of the second data line on the substrate.

5. The array substrate as claimed in claim 1 , wherein a projection of the second data line on the substrate is located at one side of a projection of the first data line on the substrate.

6. A display panel, comprising an array substrate, wherein the array substrate comprises:
a substrate; and
a source/drain layer disposed at one side of the substrate, wherein the source/drain layer is etched to form a first data line; and
wherein the array substrate comprises a second data line, and a distance between connecting holes of the first data line and the second data line is at least same as a length of one sub-pixel, wherein the array substrate comprises a first metal layer, a second metal layer, and an interlayer insulating layer; the interlayer insulating layer is disposed between the second metal layer and the source/drain layer, the second metal layer is etched to form a second electrode plate of a capacitor and the second data line, a first through-hole is formed on the interlayer insulating layer, and the second data line is connected to the first data line through the first through-hole, wherein the array substrate comprises an active layer, the source/drain layer is etched to form compensation signal lines, a direction of the compensation signal lines is same as a direction of the first data line, and the compensation signal lines are connected to the active layer through the connecting hole, wherein the interlayer insulating layer comprises a second through-hole, the source/drain layer is etched to form power voltage lines, and adjacent columns of the power voltage lines are respectively connected to opposite sides of the second electrode plate through the second through-hole, wherein the first metal layer is etched to form scanning lines, a first electrode plate of the capacitor, and other compensation signal lines, and a direction of the scanning lines is same as a direction of the other compensation signal lines.

7. The display panel as claimed in claim 6 , wherein the display panel comprises an organic light-emitting layer diode (OLED) display panel.

8. The display panel as claimed in claim 6 , wherein the display panel comprises a liquid crystal display panel.

9. The display panel as claimed in claim 6 , wherein a distance of adjacent connecting holes between the first data line and the second data line is same as twice of a sum of a length of the sub-pixel and a distance between adjacent sub-pixels.

10. The display panel as claimed in claim 6 , a distance of adjacent connecting holes between the first data line and the second data line is same as a sum of a length of the sub-pixel and a distance between adjacent sub-pixels.

11. The display panel as claimed in claim 6 , wherein a projection of the first data line on the substrate overlaps a projection of the second data line on the substrate.

12. The display panel as claimed in claim 6 , wherein a projection of the second data line on the substrate is located at one side of a projection of the first data line on the substrate.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Guo Wenjun

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F2201/506

  Repairing, e.g. with redundant arrangement against defective part · CPC title

• G02F1/136263 Primary

  Line defects · CPC title