Capacitor

Patent metadata

Field	Value
Publication number	US-11217395-B2
Application number	US-201916448366-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Jul 26, 2017
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.

First claim

The invention claimed is:

1. A capacitor comprising:
a substrate;
a lower electrode on the substrate, the lower electrode having an upper surface opposite the substrate and side surfaces extending from the upper surface toward the substrate;
a dielectric film on the upper surface and side surfaces of the lower electrode;
a first upper electrode on a first part of the dielectric film;
a second upper electrode on a second part of the dielectric film;
a protective layer covering the lower electrode and the first upper electrode and the second upper electrode;
a first external electrode that penetrates the protective layer and is electrically connected to the first upper electrode, and wherein the first external electrode is formed only in a first region defined by a first periphery of the first upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate; and
a second external electrode that penetrates the protective layer and is electrically connected to the second upper electrode, and wherein the second external electrode is formed only in a second region defined by a second periphery of the second upper electrode in the plan view of the capacitor viewed from the upper surface thereof towards the substrate.

2. The capacitor according to claim 1 , wherein
the lower electrode includes a first lower electrode and a second lower electrode,
the first upper electrode covers a part of the first lower electrode, and
the second upper electrode covers a part of the second lower electrode.

3. The capacitor according to claim 2 , further comprising a third upper electrode that extends across the first lower electrode and the second lower electrode.

4. The capacitor according to claim 1 , further comprising an insulating film between the substrate and the lower electrode.

5. A capacitor comprising:
a substrate;
a first lower electrode on the substrate;
a second lower electrode on the substrate and separate from the first lower electrode;
a dielectric film on the first lower electrode and the second lower electrode;
an upper electrode on a part of the dielectric film and that extends across the first lower electrode and the second lower electrode;
a protective layer covering the first lower electrode, the second lower electrode, and the upper electrode;
a first external electrode that penetrates the protective layer and is electrically connected to the first lower electrode; and
a second external electrode that penetrates the protective layer and is electrically connected to the second lower electrode,
wherein the first external electrode and the second external electrode are formed so as not to overlap with the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.

6. The capacitor according to claim 5 , further comprising an insulating film between the substrate and the first lower electrode and the second lower electrode.

7. A method of manufacturing a capacitor, the method comprising:
forming a lower electrode on a substrate, the lower electrode having an upper surface opposite the substrate and side surfaces extending from the upper surface toward the substrate;
forming a dielectric film on the upper surface and side surfaces of the lower electrode;
forming a first upper electrode on a first part of the dielectric film;
forming a second upper electrode on a second part of the dielectric film;
covering the lower electrode and the first upper electrode and the second upper electrode with a protective layer;
forming a first external electrode only in a first region defined by a first periphery of the first upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate, the first external electrode penetrating the protective layer and being electrically connected to the first upper electrode;
forming a second external electrode only in a second region defined by a second periphery of the second upper electrode in the plan view of the capacitor viewed from the upper surface thereof towards the substrate, the second external electrode penetrating the protective layer and being electrically connected to the second upper electrode.

8. The method of manufacturing a capacitor according to claim 7 , wherein
the lower electrode is formed so as to include a first lower electrode and a second lower electrode,
the first upper electrode is formed in a location that covers a part of the first lower electrode, and
the second upper electrode is formed in a location that covers a part of the second lower electrode.

9. The method of manufacturing a capacitor according to claim 8 , further comprising forming a third upper electrode that extends across the first lower electrode and the second lower electrode.

10. The method of manufacturing a capacitor according to claim 7 , further comprising forming an insulating film between the substrate and the lower electrode.

Assignees

• Murata Manufacturing Co

Inventors

• Harada Masatomi
• Izumitani Junko
• Kagawa Takeshi
• Matsubara Hiroshi

Classifications

• H01G4/33 Primary

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01G4/228

  Terminals · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title