Pixel driving circuit, driving method thereof, and display panel applied thereof

US11217155B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11217155-B1
Application numberUS-201916627371-A
CountryUS
Kind codeB1
Filing dateDec 24, 2019
Priority dateDec 4, 2019
Publication dateJan 4, 2022
Grant dateJan 4, 2022

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel driving circuit, a driving method thereof, and a display panel applied thereof, which comprise three thin film transistors are provided. A control terminal, a first terminal, and a second terminal of a first thin film transistor are respectively electrically coupled to a first node, a high preset potential, and a second node. A control terminal, a first terminal, and a second terminal of a second thin film transistor are respectively electrically connected to a scan line, the first node, and a data line. A control terminal, a first terminal, and a second terminal of a third thin film transistor are respectively electrically connected to a scan line, a third node, and the second node.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel driving circuit, comprising: a first thin film transistor, wherein a control terminal of the first thin film transistor is electrically coupled to a first node, a first terminal of the first thin film transistor is used for connecting to a high preset potential, and a second terminal of the first thin film transistor is electrically coupled to a second node; a second thin film transistor, wherein a control terminal of the second thin film transistor is electrically coupled to a scan line, a first terminal of the second thin film transistor is electrically coupled to the first node, and a second terminal of the second thin film transistor is electrically coupled to a data line; a third thin film transistor, wherein a control terminal of the third thin film transistor is electrically coupled to the scan line, a first terminal of the third thin film transistor is electrically coupled to a third node, and a second terminal of the third thin film transistor is electrically coupled to the second node; a fourth thin film transistor, wherein a control terminal of the fourth thin film transistor receives a frequency signal, a first terminal of the fourth thin film transistor is used for connecting to a low preset potential, and a second terminal of the fourth thin film transistor is electrically coupled to the third node; a fifth thin film transistor, wherein a control terminal of the fifth thin film transistor is electrically connected to a red pixel data line, a first terminal of the fifth thin film transistor is electrically coupled to a fourth node, and a second terminal of the fifth thin film transistor is electrically coupled to the third node; a sixth thin film transistor, wherein a control terminal of the sixth thin film transistor is electrically connected to a green pixel data line, a first terminal of the sixth thin film transistor is electrically coupled to the fourth node, and a second terminal of the sixth thin film transistor is electrically coupled to the third node; a seventh thin film transistor, wherein a control terminal of the seventh thin film transistor is electrically connected to a blue pixel data line, a first terminal of the seventh thin film transistor is electrically coupled to the fourth node, and a second terminal of the seventh thin film transistor is electrically coupled to the third node; and a storage capacitor, wherein one terminal of the storage capacitor is electrically coupled to the first node, and another terminal of the storage capacitor is electrically coupled to the second node. 2. The pixel driving circuit as claimed in claim 1 , comprising a red light-emitting diode, one terminal of the red light-emitting diode is electrically coupled to the third node, and another terminal of the red light-emitting diode is electrically coupled to the low preset potential. 3. The pixel driving circuit as claimed in claim 1 , comprising a green light-emitting diode, one terminal of the green light-emitting diode is electrically coupled to the third node, and another terminal of the green light-emitting diode is electrically coupled to the low preset potential. 4. The pixel driving circuit as claimed in claim 1 , comprising a blue light-emitting diode, one terminal of the blue light-emitting diode is electrically coupled to the third node, and another terminal of the blue light-emitting diode is electrically coupled to the low preset potential. 5. A display panel, comprising a first substrate and a second substrate disposed opposite to the first substrate, wherein the first substrate comprises the pixel driving circuit as claimed in claim 1 . 6. The display panel as claimed in claim 5 , wherein the display panel comprises a red light-emitting diode, one terminal of the red light-emitting diode is electrically coupled to the third node, and another terminal of the red light-emitting diode is electrically coupled to the low preset potential. 7. The display panel as claimed in claim 5 , comprising a green light-emitting diode, one terminal of the green light-emitting diode is electrically coupled to the third node, and another terminal of the green light-emitting diode is electrically coupled to the low preset potential. 8. The display panel as claimed in claim 5 , comprising a blue light-emitting diode, one terminal of the blue light-emitting diode is electrically coupled to the third node, and another terminal of the blue light-emitting diode is electrically coupled to the low preset potential. 9. A driving method of a pixel driving circuit, comprising: providing a first thin film transistor, wherein a control terminal of the first thin film transistor is electrically coupled to a first node, a first terminal of the first thin film transistor is used for connecting to a high preset potential, and a second terminal of the first thin film transistor is electrically coupled to a second node; providing a second thin film transistor, wherein a control terminal of the second thin film transistor is electrically coupled to a scan line, a first terminal of the second thin film transistor is electrically coupled to the first node, and a second terminal of the second thin film transistor is electrically coupled to a data line; providing a third thin film transistor, wherein a control terminal of the third thin film transistor is electrically coupled to the scan line, a first terminal of the third thin film transistor is electrically coupled to a third node, and a second terminal of the third thin film transistor is electrically coupled to the second node; providing a fourth thin film transistor, wherein a control terminal of the fourth thin film transistor receives a frequency signal, a first terminal of the fourth thin film transistor is used for connecting to a low preset potential, and a second terminal of the fourth thin film transistor is electrically coupled to the third node; providing a fifth thin film transistor, wherein a control terminal of the fifth thin film transistor is electrically connected to a red pixel data line, a first terminal of the fifth thin film transistor is electrically coupled to a fourth node, and a second terminal of the fifth thin film transistor is electrically coupled to the third node; providing a sixth thin film transistor, wherein a control terminal of the sixth thin film transistor is electrically connected to a green pixel data line, a first terminal of the sixth thin film transistor is electrically coupled to the fourth node, and a second terminal of the sixth thin film transistor is electrically coupled to the third node; providing a seventh thin film transistor, wherein a control terminal of the seventh thin film transistor is electrically connected to a blue pixel data line, a first terminal of the seventh thin film transistor is electrically coupled to the fourth node, and a second terminal of the seventh thin film transistor is electrically coupled to the third node; and providing a storage capacitor, wherein one terminal of the storage capacitor is electrically coupled to the first node, and another terminal of the storage capacitor is electrically coupled to the second node. 10. The driving method of the pixel driving circuit as claimed in claim 9 , comprising providing a red light-emitting diode, wherein one terminal of the red light-emitting diode is electrically coupled to the third node, and another terminal of the red light-emitting diode is electrically coupled to the low preset potential. 11. The driving method of the pixel driving circuit as claimed in claim 9 , comprising providing a green light-emitting diode, wherein one terminal of the green light-emitting diode is electrically coupled to the third

Assignees

Inventors

Classifications

  • Field-sequential colour display · CPC title

  • Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements · CPC title

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

  • with pixel circuitry controlling the current through the light-emitting element · CPC title

  • G09G3/3225Primary

    using an active matrix · CPC title

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What does patent US11217155B1 cover?
A pixel driving circuit, a driving method thereof, and a display panel applied thereof, which comprise three thin film transistors are provided. A control terminal, a first terminal, and a second terminal of a first thin film transistor are respectively electrically coupled to a first node, a high preset potential, and a second node. A control terminal, a first terminal, and a second terminal o…
Who is the assignee on this patent?
Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 04 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).