High rate receiver circuit

Patent metadata

Field	Value
Publication number	US-11212043-B2
Application number	US-202016824353-A
Country	US
Kind code	B2
Filing date	Mar 19, 2020
Priority date	Sep 22, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.

First claim

What is claimed is:

1. A receiver circuit comprising:
a decoder for decoding received data, wherein the receiver circuit is configured to receive the received data in transport blocks where each transport block comprises a set of individually decodable code blocks;
at least one on-chip First In First Out (FIFO) memory;
a Layer 2 decipher unit;
a buffer memory; and
a controller;

wherein the decoder is configured to:
store a correctly decoded code block in said at least one on-chip FIFO memory; and
when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory; and

wherein the Layer 2 decipher unit is configured to in a sequential deciphering process:
sequentially and in a consecutive order receive decoded code blocks from the at least one on-chip FIFO memory and decipher correctly decoded code blocks; and
when the controller indicates to the Layer 2 decipher unit that a code block has been incorrectly decoded by the decoder, stop the sequential deciphering process; and
when the controller indicates to the Layer 2 decipher unit that a previously incorrectly decoded code block later has been correctly decoded by the decoder, continue the sequential deciphering process by deciphering the previously incorrectly decoded code block and by retrieving any code blocks of the same transport block stored in the buffer memory transferred via the at least one on-chip FIFO memory for sequentially deciphering said retrieved code blocks in a consecutive order.

2. The receiver circuit according to claim 1 , wherein the decoder is configured to move correctly decoded blocks of a transport block to the at least one on-chip FIFO memory as long as all previous code blocks from the transport block are correctly decoded.

3. The receiver circuit according to claim 1 , wherein the receiver circuit is configured to receive the code blocks in a consecutive order.

4. The receiver circuit according to claim 1 , wherein the receiver circuit is configured to request re-transmission of an incorrectly decoded code block using a hybrid automatic repeat request (HARQ) process.

5. The receiver circuit according to claim 1 , wherein the buffer memory is an off-chip memory.

6. The receiver circuit according to claim 1 , wherein multiple on-chip FIFO memories are provided and wherein different parallel received transport blocks are associated with a separate on-chip FIFO memory.

7. The receiver circuit according to claim 6 , wherein a configurable number of on-chip FIFO memories are provided.

8. The receiver circuit according to claim 1 , wherein the decipher unit is configured to store a deciphered version of a transport block in a system memory of the receiver circuit when all code blocks of the transport block have been deciphered.

9. The receiver circuit according to claim 8 , wherein the buffer memory is a part of the system memory.

10. The receiver circuit according to claim 4 , wherein the Layer 2 decipher unit is configured to continue deciphering code blocks associated with another HARQ process while waiting for the incorrectly decoded code block to be correctly decoded by the decoder.

11. A method for a receiver circuit comprising:
decoding code blocks, wherein the receiver circuit is configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks;
storing a correctly decoded code block in an on-chip First In First Out (FIFO) memory;
when a code block of a transport block is incorrectly decoded, storing any subsequent correctly decoded code block of the same transport block in a buffer memory;
performing a sequential deciphering process comprising:
sequentially and in a consecutive order receiving decoded code blocks from the on-chip FIFO memory and deciphering correctly decoded code blocks in a consecutive order,
upon an indication that a code block has been incorrectly decoded stopping the sequential deciphering process, and
upon an indication that a previously incorrectly decoded code block later has been correctly decoded, continuing the sequential deciphering process by deciphering the previously incorrectly decoded code block and by retrieving any code blocks of the same transport block stored in the buffer memory transferred via the on-chip FIFO memory for sequentially deciphering said retrieved code blocks in a consecutive order.

Assignees

• Huawei Tech Co Ltd

Inventors

• Lundgren Thomas
• Lindoff Bengt

Classifications

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H04L1/1835 Primary

  Buffer management · CPC title

• H04L1/1812

  Hybrid protocols; Hybrid automatic repeat request [HARQ] · CPC title

• H04B1/16

  Circuits · CPC title

• H04L1/0061

  Error detection codes · CPC title