Method for forming an insulation layer in a semiconductor body and transistor device

Patent metadata

Field	Value
Publication number	US-11211483-B2
Application number	US-201916588003-A
Country	US
Kind code	B2
Filing date	Sep 30, 2019
Priority date	Oct 2, 2018
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.

First claim

The invention claimed is:

1. A method, comprising:
forming a trench in a first surface in an edge region of a semiconductor body;
forming an insulation layer in the trench and on the first surface of the semiconductor body;
planarizing the insulation layer so that a trench insulation layer that fills the trench remains, and
forming a plurality of transistor cells in an inner region adjoining the edge region,
wherein forming the insulation layer comprises a thermal oxidation process,
wherein the trench is completely filled by the trench insulation layer after completing the
formation of the transistor cells.

2. The method of claim 1 , wherein forming the trench comprises forming the trench such that it surrounds an inner region adjoining the edge region.

3. The method of claim 1 ,
wherein planarizing the insulation layer comprises at least partially removing the insulation layer from above the first surface of the semiconductor body.

4. The method of claim 3 , wherein at least partially removing the insulation layer from above the first surface of the semiconductor body comprises completely removing the insulation layer from above the first surface of the semiconductor body.

5. The method of claim 3 , wherein at least partially removing the insulation layer from above the first surface of the semiconductor body comprises a polishing process.

6. The method of claim 3 , wherein at least partially removing the insulation layer from above the first surface of the semiconductor body comprises:
removing sections of the insulation layer from above the first surface by an etching process such that residuals of the insulation layer that protrude from the semiconductor body remain; and
at least partially removing the residuals by a polishing process.

7. The method of claim 6 , further comprising:
forming at least one of a further oxide layer and a nitride layer on uncovered sections of the first surface before the polishing process,
wherein the at least one of the further oxide layer and a nitride layer acts as a stop layer of the polishing process.

8. The method of claim 6 , wherein the polishing process partially removes the trench insulation layer.

9. The method of claim 1 , further comprising:
before forming the insulation layer, forming a plurality of first implanted regions each of the first implanted regions comprising dopant atoms of a first doping type and a plurality of second implanted regions each of the second implanted regions comprising dopant atoms of a second doping type in the semiconductor body.

10. The method of claim 9 , wherein forming the plurality of first implanted regions and the plurality of second implanted regions comprises:
forming a plurality of epitaxial layers one above the other;
forming a plurality of trenches in at least some of the plurality of epitaxial layers before forming a respective next one of the plurality of epitaxial layers; and
introducing first type dopant atoms at least into first sidewalls of the plurality of trenches and introducing second type dopant atoms at least into second sidewalls of the plurality of trenches.

11. The method of claim 10 ,
wherein introducing first type dopant atoms at least into first sidewalls of the plurality of trenches comprises introducing first type dopant atoms into both first sidewalls and second sidewalls of the plurality of trenches, and
wherein introducing second type dopant atoms at least into first sidewalls of the plurality of trenches comprises introducing second type dopant atoms into both first sidewalls and second sidewalls of the plurality of trenches.

12. The method of claim 1 , further comprising:
forming a field electrode on the trench insulation layer.

13. The method of claim 1 , wherein the first surface is entirely oxidized in the thermal oxidation process.

14. The method of claim 1 , wherein a thickness of a thermal oxidation layer formed by the thermal oxidation process is between 0.2 times and 1.3 times a depth of the trench.

15. The method of claim 1 ,
wherein an aspect ratio of the trench is less than 1.

16. A transistor device, comprising:
a plurality of superjunction transistor cells in an inner region of a semiconductor body;
a trench insulation layer arranged in an edge region of the semiconductor body and extending in a vertical direction of the semiconductor body from a first surface of the semiconductor body into the semiconductor body,
wherein the edge region comprises a trench that is exclusively filled by the trench insulation layer.

17. The transistor device of claim 16 , wherein a depth of the trench insulation layer in the vertical direction is between 0.1 micrometers and 0.5 micrometers.

18. The transistor device of claim 16 , further comprising:
a further insulation layer formed on top of the trench insulation layer.

19. The transistor device of claim 16 , further comprising:
an electrically conducting field plate either on top of a surface of the trench insulation layer or on top of a surface of the further insulation layer,
wherein the field plate is connected to a source node or a gate of the transistor device.

20. The transistor device of claim 16 , wherein the trench insulation layer forms a closed loop around the inner region.

21. The transistor device of claim 16 , wherein a depth of the trench insulation layer in the vertical direction is between 0.1 micrometers and 0.5 micrometers.

22. The method of claim 1 , wherein the edge region of the semiconductor body extends from an outer edge of the semiconductor body to the inner region, and wherein the trench is the only trench in the edge region.

23. The transistor device of claim 16 , wherein the edge region of the semiconductor body extends from an outer edge of the semiconductor body to the inner region, and wherein the trench is the only trench in the edge region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Weber Hans
• Fachmann Christian
• Hirler Franz
• Kaindl Winfried
• Rochel Markus

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title