Semiconductor structure and method for forming same

Patent metadata

Field	Value
Publication number	US-11211478-B2
Application number	US-202016993689-A
Country	US
Kind code	B2
Filing date	Aug 14, 2020
Priority date	Feb 28, 2020
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a base;
forming a discrete core layer on the base;
forming a spacer on a sidewall of the core layer;
removing the core layer;
after the core layer is removed, patterning the base using the spacer as a mask to form a fin, where the fin comprises a device fin and a dummy fin;
removing the spacer; and
performing doping removal on the dummy fin one or more times, removing the dummy fin, where the step of the doping removal comprises:
forming a shielding layer to cover the device fin, the shielding layer having an opening located above the dummy fin and corresponding to a position of the dummy fin;
after forming the shielding layer, performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin;
removing the shielding layer; and
after removing the shielding layer, removing the ion-doped dummy fin.

2. The method for forming a semiconductor structure according to claim 1 , wherein:
in the step of forming the spacer, the spacer is used as a mask for patterning the base to form the fin, and a position of the spacer corresponds to a position of the fin, wherein a spacer for forming the device fin is a mask spacer, and a spacer for forming the dummy fin is a dummy mask spacer, where the dummy mask spacer comprises a first dummy spacer consisting of a plurality of adjacent spacers and a second dummy spacer consisting of a single spacer;
after the core layer is removed and before the base is patterned, the method for forming a semiconductor structure further comprises: removing the second dummy spacer; and
during patterning of the base, the base is patterned using the spacer as a mask, the device fin is formed at a position corresponding to a position of the mask spacer, and the dummy fin is formed at positions corresponding to positions of a plurality of dummy mask spacers in the first dummy spacer.

3. The method for forming a semiconductor structure according to claim 1 , wherein in the step of performing ion doping on the entire dummy fin or a part of the dummy fin in thickness, doped ions comprise argon ions, boron ions, or arsenic ions.

4. The method for forming a semiconductor structure according to claim 1 , wherein the step of removing the dummy fin comprises:
performing doping removal once, the doping removal comprising:
performing ion doping on the entire dummy fin; and
removing the ion-doped dummy fin.

5. The method for forming a semiconductor structure according to claim 4 , wherein in the step of performing ion doping on the entire dummy fin, an ion doping concentration in the dummy fin is 1.0E18 atom/cm 3 to 1.0E22 atom/cm 3 .

6. The method for forming a semiconductor structure according to claim 4 , wherein a process for performing ion doping on the entire dummy fin comprises an ion injection process.

7. The method for forming a semiconductor structure according to claim 6 , wherein a parameter of the ion injection process comprises: an injection energy of 10 KeV to 200 KeV and an injection angle of 0°.

8. The method for forming a semiconductor structure according to claim 1 , wherein:
during patterning of the base, a hard mask layer is further formed on the top of the fin; and
in the step of forming the shielding layer, the dummy fin is exposed from the opening, or the hard mask layer on the dummy fin is exposed from the opening.

9. The method for forming a semiconductor structure according to claim 1 , wherein in the step of forming the shielding layer, a thickness of the shielding layer on the device fin is 500 Å to 2000 Å.

10. The method for forming a semiconductor structure according to claim 1 , wherein in the step of removing the ion-doped dummy fin, the etching selection ratio of the dummy fin to the device fin is at least 10:1.

11. The method for forming a semiconductor structure according to claim 1 , wherein a process for removing the ion-doped dummy fin comprises a wet etching process or a plasma etching process.

12. The method for forming a semiconductor structure according to claim 11 , wherein the ion-doped dummy fin is removed using a wet etching process, where an etching solution in the wet etching process comprises a mixed solution of hydrofluoric acid, nitric acid, and acetic acid.

13. The method for forming a semiconductor structure according to claim 12 , wherein a parameter of the wet etching process comprises:
a volume ratio of hydrofluoric acid, nitric acid to acetic acid in the mixed solution of hydrofluoric acid, nitric acid, and acetic acid is 1:1:1 to 1:4:8.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Shanghai International Corporation
• Semiconductor Mfg Beijing International Corporation

Inventors

• Erhu Zheng
• Panpan Liu

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10P30/208

  of electrically inactive species · CPC title