Power island segmentation for selective bond-out

Patent metadata

Field	Value
Publication number	US-11211329-B2
Application number	US-202016832498-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 13, 2018
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.

First claim

What is claimed is:

1. A semiconductor chip comprising a semiconductor die formed on a substrate, the semiconductor die comprising:
a first plurality of power lines formed in one or more layers on the substrate;
a second plurality of power lines formed in the one or more layers on the substrate and configured to be electrically isolated from the first plurality of power lines;
a first circuit block formed on the substrate and electrically connected to the first plurality of power lines configured to supply power to the first circuit block; and
a second circuit block formed on the substrate and electrically connected to the second plurality of power lines configured to supply power to the second circuit block, the second circuit block coupled to at least one external circuit connection electrically isolated from the first circuit block,
wherein
the first plurality of power lines is formed over the first circuit block,
the second plurality of power lines is formed over the second circuit block, and
the first plurality of power lines and the second plurality of power lines are formed in at least one same layer of the one or more layers on the substrate;
one or more first signal pins formed on the substrate and configured to be communicatively coupled to receive first one or more signals external to the semiconductor chip; and
one or more second signal pins formed on the substrate and configured to be communicatively coupled to receive second one or more signals external to the semiconductor chip.

2. The semiconductor chip of claim 1 , wherein the first plurality of power lines and the second plurality of power lines are configured to be switched on and off.

3. The semiconductor chip of claim 1 , further comprising a third circuit block configured to selectively supply power to the first plurality of power lines and the second plurality of power lines.

4. The semiconductor chip of claim 1 , wherein the third circuit block is configured as a switch.

5. The semiconductor chip of claim 1 , wherein the second circuit block is configured to be non-operational.

6. The semiconductor chip of claim 5 , wherein the first circuit block is coupled to at least one of the one or more first signal pins and at least one of the one or more second signal pins.

7. The semiconductor chip of claim 6 , wherein the second circuit block is coupled to at least one of the one or more second signal pins and is not coupled to any of the one or more first signal pins.

8. The semiconductor chip of claim 7 , wherein the one or more first signal pins are configured to receive power from a power supply and the one or more second signal pins are configured to receive a ground supply.

9. The semiconductor chip of claim 8 , wherein the second plurality of power lines does not receive power from the power supply.

10. The semiconductor chip of claim 1 , wherein the first plurality of power lines is configured as a first power mesh and the second plurality of power lines is configured as a second power mesh.

11. The semiconductor chip of claim 10 , wherein the first power mesh is segmented by providing a first layer of connections configured to connect to a ground supply and a second layer of connections configured to connect to a power supply, and the second power mesh is segmented by providing a third layer of connections configured to connect to the ground supply and a fourth layer of connections configured to connection to the power supply.

12. The semiconductor chip of claim 11 , wherein the third layer of connections and the fourth layer of connections are not coupled to the power supply.

13. The semiconductor of claim 12 , wherein the third layer of connections and the fourth layer of connections are coupled to the ground supply.

14. The semiconductor chip of claim 1 , wherein a flow of current through the first circuit block does not induce a leakage current in the second circuit block.

15. The semiconductor chip of claim 1 , wherein the first circuit block and second circuit block are instantiated on a ball grid array.

16. The semiconductor chip of claim 15 , wherein the second circuit block is connected to a ground supply by a plurality of ball connections.

17. The semiconductor chip of claim 1 , further comprising:
a first plurality of external circuit connections communicatively coupled to the first circuit block and communicatively isolated from the second circuit block; and
a second plurality of external circuit connections communicatively coupled to the second circuit block and communicatively isolated from the first circuit block.

18. The semiconductor chip of claim 17 , further comprising a plurality of external devices coupled to the first plurality of external circuit connections.

19. The semiconductor chip of claim 17 , wherein the first plurality of external circuit connections are physically isolated from the second circuit block and the second plurality of external circuit connections are physically isolated from the first circuit block.

Assignees

• Kioxia Corp

Inventors

• Kerr Benjamin

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title