Semiconductor structure and method for forming same

Patent metadata

Field	Value
Publication number	US-11211260-B2
Application number	US-202016861784-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Aug 14, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor structure and a method for forming same are provided, the forming method including: providing a base including a plurality of adjacent device unit regions, an initial device gate structure spanning a plurality of device unit regions being formed on the base; etching a portion of the initial device gate structure in thickness at a junction between the adjacent device unit regions to form a top opening; forming a spacer layer on a side wall of the top opening; etching a remainder of the initial device gate structure exposed from the spacer layer, and forming a bottom opening exposed from the base within the remainder of the initial device gate structure, the remainder of the initial device gate structure being used as a device gate structure; and forming an isolation structure within the top opening and the bottom opening. The spacer layer is configured to adjust a width of the bottom opening, so that the width of the bottom opening is less than a width of the top opening. Therefore, the width of the top opening can be increased properly to enlarge a process window in which the top opening is formed, thereby better implementing isolation between the adjacent device unit regions and improving integrity of the device gate structure, further helping improve performance of a transistor.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a base, where the base comprises a plurality of device unit regions that are adjacent to each other, an initial device gate structure is formed on the base, and the initial device gate structure spans a plurality of device unit regions;
forming a mask layer on the initial device gate structure, where a mask opening is formed within the mask layer;
after forming the mask layer on the initial device gate structure, etching a portion of the initial device gate structure in thickness at a junction between adjacent device unit regions of the plurality of device unit regions to form a top opening within the initial device gate structure, wherein etching the portion of the initial device gate structure comprises:
using the mask layer as a mask to etch the portion of the initial device gate structure in thickness exposed from the mask opening;

forming a spacer layer on a side wall of the top opening and on a side wall of the mask opening;
etching a remainder of the initial device gate structure exposed from the spacer layer to form a bottom opening exposed from the base within the remainder of the initial device gate structure, where the bottom opening is in communication with the top opening, and the remainder of the initial device gate structure is used as a device gate structure; and
forming an isolation structure within the top opening and the bottom opening.

2. The method for forming a semiconductor structure according to claim 1 , wherein:
the step of forming the spacer layer comprises: forming a spacer film, where the spacer film conformally covers the side wall of the mask opening, a bottom and the side wall of the top opening, and a top of the mask layer; and
removing spacer films on the top of the mask layer and the bottom of the top opening, and retaining spacer films on the side wall of the mask opening and on the side wall of the top opening as the spacer layer.

3. The method for forming a semiconductor structure according to claim 2 , wherein the spacer film is formed using an atomic layer deposition process.

4. The method for forming a semiconductor structure according to claim 1 , wherein:
the step of forming an isolation structure within the top opening and the bottom opening comprises:
filling an isolation material layer within the mask opening, the top opening, and the bottom opening, where the isolation material layer further covers a top of the mask layer;
etching back the isolation material layer, and removing the isolation material layer higher than the top of the mask layer; and
after the etch-back processing, flattening the mask layer, the spacer layer, and a remainder of the isolation material layer using a chemical mechanical polishing process, and retaining the remainder of the isolation material layer within the top opening and the bottom opening as the isolation structure.

5. The method for forming a semiconductor structure according to claim 4 , wherein the isolation material layer is formed using an atomic layer deposition process.

6. The method for forming a semiconductor structure according to claim 1 , wherein the portion of the initial device gate structure in thickness at the junction between the adjacent device unit regions is etched using a dry etching process.

7. The method for forming a semiconductor structure according to claim 1 , wherein the remainder of the initial device gate structure exposed from the spacer layer is etched using a dry etching process.

8. The method for forming a semiconductor structure according to claim 1 , wherein a range of a thickness of the spacer layer is from 0.5 nm to 20 nm along a direction perpendicular to the side wall of the top opening.

9. The method for forming a semiconductor structure according to claim 1 , wherein the spacer layer is made of a dielectric material.

10. The method for forming a semiconductor structure according to claim 1 , wherein:
in the step of providing the base, the initial device gate structure is an initial metal gate structure; and
in the step of etching a remainder of the initial device gate structure exposed from the spacer layer, the device gate structure is a metal gate structure.

11. A method for forming a semiconductor structure, comprising:
providing a base, where the base comprises a plurality of device unit regions that are adjacent to each other, an initial device gate structure is formed on the base, and the initial device gate structure spans a plurality of device unit regions and comprises an initial gate electrode layer;
etching a portion of the initial device gate structure in thickness at a junction between adjacent device unit regions of the plurality of device unit regions to form a top opening within the initial device gate structure, wherein a depth of the top opening accounts for 10% to 80% of a thickness of the initial gate electrode layer on the top of the fin;
forming a spacer layer on a side wall of the top opening;
etching a remainder of the initial device gate structure exposed from the spacer layer to form a bottom opening exposed from the base within the remainder of the initial device gate structure, where the bottom opening is in communication with the top opening, and the remainder of the initial device gate structure is used as a device gate structure; and
forming an isolation structure within the top opening and the bottom opening;
wherein in the step of providing the base, the base further comprises a substrate and a fin protruding from the substrate, along a direction perpendicular to a side wall of the fin, where the base comprises a plurality of adjacent device units;
wherein the initial device gate structure spans fins of the plurality of device unit regions, and covers a portion of a top and a portion of a side wall of the fin; and
wherein in the step of etching a remainder of the initial device gate structure exposed from the spacer layer, the remainder of the initial device gate structure between the adjacent fins is etched at the junction between the adjacent initial device unit regions.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Shanghai International Corporation
• Semiconductor Mfg Beijing International Corporation

Inventors

• Long Zhang Cheng

Classifications

• H10P50/69 Primary

  using masks for semiconductor materials · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title