Semiconductor structure

Patent metadata

Field	Value
Publication number	US-11211255-B2
Application number	US-202016783450-A
Country	US
Kind code	B2
Filing date	Feb 6, 2020
Priority date	Sep 22, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A semiconductor structure is provided. The semiconductor structure includes: a substrate; and a functional layer, on the substrate. The substrate includes a device region. The semiconductor structure further includes a plurality of discrete sidewall spacers, on the functional layer in the device region. Adjacent sidewall spacers are spaced apart by a first gap and a second gap, and the first gap and the second gap are alternately arranged. The semiconductor structure further includes: a core layer on a sidewall surface of one side of the sidewall spacer; a second opening in the functional layer at a bottom of the second gap exposed by the sidewall spacer and the core layer; and a first opening in the functional layer at a bottom of the first gap. The core layer is disposed in the second gap.

First claim

What is claimed is:

1. A semiconductor structure, comprising: a substrate, wherein the substrate includes a device region; a functional layer, on the substrate; a plurality of discrete sidewall spacers, on the functional layer in the device region, wherein adjacent sidewall spacers are spaced apart by a first gap and a second gap, and the first gap and the second gap are alternately arranged; a core layer on a sidewall surface of one side of the sidewall spacer, wherein the core layer is disposed in the second gap; a second opening in the functional layer at a bottom of the second gap exposed by the sidewall spacer and the core layer; a first opening in the functional layer at a bottom of the first gap; a second interconnection line in the second opening; and a first interconnection line in the first opening, wherein the second and first interconnection lines are made of copper.

2. The semiconductor structure according to claim 1 , wherein the substrate further includes a preserved region.

3. The semiconductor structure according to claim 2 , wherein a third opening is formed in the functional layer in the preserved region.

4. The semiconductor structure according to claim 1 , further including a device layer on the substrate, wherein the device layer is made of a material different from the functional layer and the function layer is formed on the device layer.

5. The semiconductor structure according to claim 4 , wherein the device layer is made of one or more of polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

6. The semiconductor structure according to claim 4 , wherein the functional layer is made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.

7. The semiconductor structure according to claim 1 , wherein the device layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and an organic dielectric material.

8. The semiconductor structure according to claim 1 , wherein the functional layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and an organic dielectric material.

9. The semiconductor structure according to claim 1 , wherein a spacing between the second opening and the first opening equals a sum of a width of core layer and a width of the plurality of discrete sidewall spacers.

10. The semiconductor structure according to claim 1 , wherein a width of the plurality of discrete sidewall spacers is in a range of approximately 18 nm-22 nm.

11. A semiconductor structure, comprising: a substrate, wherein the substrate includes a device region; a functional layer, on the substrate; a plurality of discrete sidewall spacers, on the functional layer in the device region, wherein adjacent sidewall spacers are spaced apart by a first gap and a second gap, and the first gap and the second gap are alternately arranged; a core layer on a sidewall surface of one side of the sidewall spacer, wherein the core layer is disposed in the second gap; a second opening in the functional layer at a bottom of the second gap exposed by the sidewall spacer and the core layer; and a first opening in the functional layer at a bottom of the first gap, wherein: a spacing between the second opening and the first opening equals a sum of a width of core layer and a width of the plurality of discrete sidewall spacers.

12. The semiconductor structure according to claim 11 , further including: a device layer on the substrate, wherein the device layer is made of a material different from the functional layer and the function layer is formed on the device layer.

13. The semiconductor structure according to claim 12 , wherein the device layer is made of one or more of polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

14. The semiconductor structure according to claim 12 , wherein the functional layer is made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.

15. The semiconductor structure according to claim 11 , wherein the device layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and an organic dielectric material.

16. The semiconductor structure according to claim 11 , wherein the functional layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and an organic dielectric material.

17. The semiconductor structure according to claim 11 , wherein: a width of the plurality of discrete sidewall spacers is in a range of approximately 18 nm-22 nm.

18. The semiconductor structure according to claim 11 , wherein the substrate further includes a preserved region and a third opening is formed in the functional layer in the preserved region.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Bei Duohui

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/287

  by chemical means · CPC title