Driving circuit of display panel, driving method thereof, and display panel

US11211027B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11211027-B2
Application numberUS-201816084027-A
CountryUS
Kind codeB2
Filing dateApr 8, 2018
Priority dateAug 7, 2017
Publication dateDec 28, 2021
Grant dateDec 28, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.

First claim

Opening claim text (preview).

What is claimed is: 1. A driving circuit of a display panel, comprising: a turn-on voltage adjusting circuit, the turn-on voltage adjusting circuit comprising: a control subcircuit; and a switching and voltage division subcircuit; the switching and voltage division sub circuit comprising: a switching subcircuit; and a basic voltage division subcircuit; wherein the switching subcircuit includes a control terminal, a first input terminal, a second input terminal and an output terminal; the control terminal of the switching subcircuit is configured to input a control signal of a corresponding resolution, the first input terminal thereof is electrically connected with an output terminal of the control subcircuit, the second input terminal is configured to access a ground power supply signal, and the output terminal thereof is electrically connected with a voltage division feedback node; and the switching subcircuit is configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node; and wherein the control subcircuit includes a first input terminal, a second input terminal and the output terminal, the first input terminal of the control subcircuit is electrically connected with the voltage division feedback node, the second input terminal thereof is configured to input an initial level signal, and the output terminal thereof is electrically connected with the first input terminal of the switching and voltage division subcircuit and is configured to output an turn-on voltage signal of the corresponding resolution. 2. The driving circuit according to claim 1 , further comprising a plurality of cascaded shift registers, wherein the turn-on voltage adjusting circuit is configured to adjust the initial level signal for turning on a pixel switch to a turn-on voltage signal matching a present resolution of the display panel, and output the turn-on voltage signal to a reference level signal terminal of each of the plurality of the cascaded shift registers; and each of the plurality of the cascaded shift registers is configured to input a scan signal corresponding to the present resolution of the display panel to a correspondingly connected gate line based on the turn-on voltage signal at the reference level signal terminal in case that the display panel performs a driving scan. 3. The driving circuit according to claim 1 , wherein the switching subcircuit comprises: a third resistor; a fourth resistor; a first switching transistor; and a second switching transistor; wherein one terminal of the third resistor is electrically connected with one terminal of the fourth resistor and configured to access the signal outputted by the output terminal of the control subcircuit, the other terminal of the third resistor is electrically connected with a source electrode of the first switching transistor; a gate electrode of the first switching transistor is respectively electrically connected with the other terminal of the fourth resistor and a drain electrode of the second switching transistor, a drain electrode of the first switching transistor is electrically connected with the voltage division feedback node; and a gate of the second switching transistor is configured to input the control signal of the corresponding resolution, and a source of the second switching transistor is configured to access the ground power supply signal. 4. The driving circuit according to claim 1 , wherein the switching subcircuit comprises: a first voltage division resistor; and a fifth switching transistor; wherein one terminal of the first voltage division resistor is configured to access the signal outputted by the output terminal of the control subcircuit, the other terminal thereof is electrically connected with a source electrode of the fifth switching transistor; and a gate electrode of the fifth switching transistor is configured to input the control signal of the corresponding resolution, and a drain electrode thereof is electrically connected with the voltage division feedback node. 5. The driving circuit according to claim 1 , wherein the basic voltage division subcircuit comprises: a first resistor; and a second resistor; wherein one terminal of the first resistor is configured to access the signal outputted by the output terminal of the control subcircuit, and the other terminal thereof is electrically connected with the voltage division feedback node; and one terminal of the second resistor is electrically connected with the voltage division feedback node, and the other terminal thereof is configured to access the ground power supply signal. 6. The driving circuit according to claim 1 , wherein the control subcircuit comprises a voltage division feedback processing subcircuit; and a voltage regulation subcircuit; a first control terminal of the voltage division feedback processing subcircuit is configured to input a pulse control signal, a second control terminal thereof is configured to input a reference signal, a first input terminal thereof is configured to input the initial level signal, a second input terminal thereof is electrically connected with the voltage division feedback node, an output terminal thereof is electrically connected with an input terminal of the voltage regulation subcircuit; and under control of the pulse control signal, the reference signal, and the voltage division feedback signal, the voltage division feedback processing subcircuit is configured to perform feedback of the initial level signal to form a corresponding coupling charging signal and output the corresponding coupling charging signal to the first input terminal of the voltage regulation subcircuit; and a second input terminal of the voltage regulation subcircuit is configured to input the initial level signal, an output terminal thereof is configured to output the turn-on voltage signal after voltage regulation; and the voltage regulation subcircuit is configured to perform voltage regulation of the initial level signal based on the coupling charging signal to form the turn-on voltage signal of the corresponding resolution and output the turn-on voltage signal. 7. The driving circuit according to claim 1 , wherein the turn-on voltage adjusting circuit comprises a plurality of switching subcircuits, and each of the plurality of switching subcircuits corresponds to a different resolution. 8. The driving circuit according to claim 1 , further comprising a common voltage adjusting circuit; wherein the common voltage adjusting circuit is configured to adjust a power supply signal for providing a common voltage to a common voltage signal matching the corresponding resolution of the display panel and output the common voltage signal. 9. The driving circuit according to claim 8 , wherein the common voltage adjusting circuit comprises a common voltage switching subcircuit; wherein a control terminal of the common voltage switching subcircuit is configured to input a switching control signal corresponding to the present resolution, a first input terminal thereof is configured to access the power supply signal, a second input terminal thereof is configured to connect with the ground power supply signal, an output terminal thereof is configured to output the common voltage signal of the corresponding resolution, and under control of the switching control signal, the common voltage switching subcircuit is configured to adjust the power supply signal to the common voltage signal of the corresponding resolution and output

Assignees

Inventors

Classifications

  • Power management, e.g. power saving · CPC title

  • Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

  • Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

  • Details of drivers for scan electrodes · CPC title

  • Vertical resolution change · CPC title

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Frequently asked questions

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What does patent US11211027B2 cover?
The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switchi…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3696. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 28 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).