Display device having at least two emission enable periods per image frame and method of driving the same

Patent metadata

Field	Value
Publication number	US-11211003-B2
Application number	US-201916524744-A
Country	US
Kind code	B2
Filing date	Jul 29, 2019
Priority date	Sep 17, 2018
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

In a display device including pixels, each of the pixels may include: a first transistor coupled to a first node, a first power supply voltage line, and a second node; and a light-emitting diode coupled to the second node and a second power supply voltage line. Each image frame may include at least two emission enable periods for the light-emitting diode, and at least one emission inhibit period between the at least two emission enable periods.

First claim

What is claimed is:

1. A display device comprising pixels, wherein each of the pixels comprises:
a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power supply voltage line, and a second electrode coupled to a second node; and
a light-emitting diode including an anode electrode coupled to the second node, and a cathode electrode coupled to a second power supply voltage line,
wherein each of image frames includes at least two emission enable periods for the light-emitting diode, and at least one emission inhibit period between the at least two emission enable periods,
wherein, during each of the at least two emission enable periods, a first power supply voltage applied to the first power supply voltage line is greater than a second power supply voltage applied to the second power supply voltage line, and
wherein, during a data voltage write operation and the at least one emission inhibit period, the first power supply voltage is less than or equal to the second power supply voltage.

2. The display device of claim 1 , further comprising:
a second transistor including a gate electrode coupled to a scan line, a first electrode coupled to the first node, and a second electrode coupled to a third node;
a first capacitor including a first electrode coupled to the first node, and a second electrode coupled to a first control line;
a third transistor including a gate electrode coupled to a second control line, a first electrode coupled to the third node, and a second electrode coupled to the second node; and
a second capacitor including a first electrode coupled to the third node, and a second electrode coupled to a data line.

3. The display device of claim 2 , wherein a first control voltage applied to the first control line during each of the at least two emission enable periods is less than the first control voltage in the at least one emission inhibit period.

4. The display device of claim 2 , wherein a first control voltage applied to the first control line during a first initialization period is less than the first control voltage in each of the at least two emission enable periods.

5. The display device of claim 4 , wherein, during at least a portion of the first initialization period, a second control voltage applied to the second control line is at a turn-on level, and a scan signal applied to the scan line is at a turn-on level.

6. The display device of claim 5 ,
wherein, during a compensation period, the second control voltage and the scan signal are at turn-on levels, and
wherein the first power supply voltage applied to the first power supply voltage line in the compensation period is greater than the first power supply voltage applied to the first power supply voltage line in the first initialization period.

7. The display device of claim 6 , wherein, during at least a portion of the first initialization period, the second control voltage is at a turn-off level, the scan signal is at the turn-on level, and the first power supply voltage is less than or equal to the second power supply voltage applied to the second power supply voltage line.

8. The display device of claim 7 ,
wherein the first control voltage in a second initialization period is less than the first control voltage in each of the at least two emission enable periods, and
wherein the first power supply voltage in the second initialization period is less than or equal to the second power supply voltage.

9. The display device of claim 8 , wherein each of the image frames sequentially includes the first initialization period, the compensation period, a data write period, the second initialization period, and the at least two emission enable periods.

10. The display device of claim 1 , wherein the first power supply voltage in each of the at least two emission enable periods is greater than the first power supply voltage in the at least one emission inhibit period.

11. The display device of claim 1 , wherein the second power supply voltage in each of the at least two emission enable periods is less than the second power supply voltage in the at least one emission inhibit period.

12. A method of driving a display device comprising pixels, each of the pixels including a driving current path including a first power supply voltage line, a first electrode and a second electrode of a first transistor, an anode electrode and a cathode electrode of a light-emitting diode, and a second power supply voltage line, the method comprising:
writing, in a data voltage write operation, a data voltage to a first electrode of a first capacitor coupled to a gate electrode of the first transistor, wherein a first power supply voltage applied to the first power supply voltage line is less than or equal to a second power supply voltage applied to the second power supply voltage line;
setting, in a first emission enable operation of the light-emitting diode, the first power supply voltage to be greater than the second power supply voltage;
setting, in an emission inhibit operation of the light-emitting diode, the first power supply voltage to be less than or equal to the second power supply voltage; and
setting, in a second emission enable operation of the light-emitting diode, the first power supply voltage to be greater than the second power supply voltage,
wherein, in each of image frames, the data voltage write operation, the first emission enable operation, the emission inhibit operation, and the second emission enable operation are sequentially performed.

13. The method of claim 12 , wherein the first power supply voltage in the first emission enable operation and the second emission enable operation is greater than the first power supply voltage in the emission inhibit operation.

14. The method of claim 12 , wherein the second power supply voltage in the first emission enable operation and the second emission enable operation is less than the second power supply voltage in the emission inhibit operation.

15. The method of claim 12 , further comprising:
applying, in a first initialization operation, a first control voltage to a first control line coupled to a second electrode of the first capacitor,
wherein the first control voltage in the first initialization operation is less than the first control voltage in the first emission enable operation and the second emission enable operation.

16. The method of claim 15 , further comprising:
diode-connecting, in a compensation operation, the first transistor,
wherein the first power supply voltage in the compensation operation is greater than the first power supply voltage in the first initialization operation.

17. The method of claim 16 , further comprising:
setting, in a second initialization operation, the first control voltage to be less than the first control voltage in the first emission enable operation and the second emission enable operation,
wherein the first power supply voltage in the second initialization operation is less than or equal to the second power supply voltage.

18. The method of claim 17 , wherein, in each of the image frames, the first initialization operation, the compensation operation, the data voltage write operation, the second initialization operation, the first emission enable operation, the emission inhibit operation, and the second emission enable operation are sequentially performed.

19. A method of driving a display device comprising pixels, each of the pixels including a driving current path including a first power supply volt

Assignees

• Samsung Display Co Ltd

Inventors

• Seo Young Wan
• Woo Min Kyu
• Lee An Su
• Lee Cheol Gon

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title