Memory appliance couplings and operations

Patent metadata

Field	Value
Publication number	US-11210240-B2
Application number	US-201916595010-A
Country	US
Kind code	B2
Filing date	Oct 7, 2019
Priority date	Apr 10, 2015
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

First claim

What is claimed:

1. A memory appliance (MA) comprising:
a local interconnect;
a host central processing unit (CPU) coupled to the local interconnect; and
a plurality of memory modules coupled to the local interconnect and each comprising a memory controller and a memory component, wherein the MA is configured to store data within the plurality of memory modules;
wherein the local interconnect is configured to:
receive a request to access the data from at least one of a first server coupled to the local interconnect of the MA through a first connection, or a second server coupled to the local interconnect of the MA through a second connection, wherein the request to access the data stored in the MA comprises an address and is received by the local interconnect through the first or second connections to bypass at least one of a network switch or an interconnect switch disposed external to the MA;
perform an address translation to translate the address to a translated memory address associated with a corresponding one of the plurality of memory modules, while bypassing the host CPU of the MA, to access the data stored in the corresponding one of the plurality of memory modules responsive to the request;
send an access request to the corresponding one of the plurality of memory modules, the access request comprising the translated memory address;
receive the data from the one of the plurality of memory modules; and
send the data from the local interconnect to the at least one of the first server and the second server in response to the request to access the data.

2. The MA of claim 1 , wherein the first and second connections are selected from the group consisting of PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark), INFINIBAND (registered trademark), and Ethernet.

3. The MA of claim 1 , wherein the network switch and the interconnect switch are selected from the group consisting of an Ethernet switch, a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark) switch, and an INFINIBAND (registered trademark) switch, and wherein the MA is disposed within a rack and the first and second server are disposed within the rack.

4. The MA of claim 1 , wherein the local interconnect is configured to control access to portions of the plurality of memory modules within the MA by the first server and the second server.

5. The MA of claim 1 , wherein the local interconnect is configured to partition portions of the plurality of memory modules within the MA.

6. A method of transferring data in a memory appliance (MA), the method comprising:
receiving, from a first server coupled to a local interconnect of the MA through a first connection and from a second server coupled to the local interconnect through a second connection, data requests to transfer data from a plurality of memory devices coupled to the local interconnect, each comprising a memory controller and a memory component, wherein the requests each comprise a respective memory address and are received by the local interconnect through the first and second connections to bypass at least one of a network switch or an interconnect switch disposed external to the MA;
configuring an engine of the local interconnect to transfer data from the plurality of memory devices to the first server and the second server through the first and second connections responsive to the data requests;
translating, by the engine of the local interconnect, the respective memory addresses associated with the data requests to translated addresses associated with corresponding ones of the plurality of memory modules, while bypassing a host central processing unit (CPU) of the memory appliance, and generate a translated memory address;
sending access requests to the plurality of memory devices, the access requests comprising the translated memory addresses;
receiving the data from the plurality of memory devices; and
sending the data from the local interconnect to the first server and the second server in response to the data requests.

7. The method of claim 6 , wherein the plurality of memory devices is disposed within the memory appliance.

8. The method of claim 6 , wherein the local interconnect is a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark) interconnect.

9. The method of claim 6 , wherein the access requests are direct memory access (DMA) requests.

10. The method of claim 6 , wherein the sending of the data is performed transparently to the CPU.

11. The method of claim 6 , wherein the sending of the data by the local interconnect bypasses the CPU.

12. The method of claim 6 , wherein the CPU receives the data requests and responsive thereto configures a request queue for the local interconnect to execute the data requests.

13. A computing device comprising:
a local interconnect comprising a processing engine;
a host central processing unit (CPU) coupled to the local interconnect; and
a plurality of memory devices coupled to the local interconnect and each comprising a memory controller and a memory component, wherein the computing device is configured to store data within the plurality of memory devices;
wherein the processing engine of the local interconnect is configured to:
receive requests to access the data from at least one of a first server coupled to the local interconnect of the computing device through a first connection, or a second server coupled to the local interconnect of the computing device through a second connection, wherein the requests to access the data stored in the MA comprise respective addresses and are received by the local interconnect through the first or second connections to bypass at least one of a network switch or an interconnect switch disposed external to the computing device;
perform an address translation to translate the respective addresses to translated memory addresses associated with corresponding ones of the plurality of memory modules, while bypassing the host CPU of the MA, to access the data stored in the corresponding ones of the plurality of memory devices responsive to the requests;
send access requests to the corresponding ones of the plurality of memory modules, the access requests comprising the translated memory addresses;
receive the data from the corresponding ones of the plurality of memory modules; and
send the data from the local interconnect to the at least one of the first server and the second server in response to the requests to access the data.

14. The computing device of claim 13 , wherein the first and second connections are selected from the group consisting of PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark), INFINIBAND (registered trademark), and Ethernet.

15. The computing device of claim 13 , wherein the network switch and the interconnect switch are selected from the group consisting of an Ethernet switch, PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark) switch, and an INFINIBAND (registered trademark) switch, and wherein the computing device is disposed within a rack and the first and second server are disposed within the rack.

16. The computing device of claim 13 , wherein the processing engine of the local interconnect is configured to control access to portions of the plurality of memory devices within the computing device by the first server and the second server.

17. The computing device of claim 13 , wherein the processing engine of the local interconnect is configured to partition portions of the plurality of memory devices within the computing device.

Assignees

• Rambus Inc

Inventors

• Fruchter Vlad
• Lowery Keith
• Uhler George Michael
• Woo Steven
• Yeung Chi-Ming (Philip)
• Lee Ronald

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title