Vector friendly instruction format and execution thereof

Patent metadata

Field	Value
Publication number	US-11210096-B2
Application number	US-202017004711-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Apr 1, 2011
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

First claim

What is claimed is:

1. An apparatus comprising:
a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, a class field, an alpha field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the class field, the alpha field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the class field, the alpha field, and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, wherein a first value in the class field specifies a first class and a second value specifies a second class, the processor including,
a decode unit to decode the occurrences of the instructions in the first instruction format follows:
distinguish the occurrences of instructions in the first instruction format that specify memory access from those that do not based on the modifier field's content in those different occurrences, wherein the beta field is interpreted as a broadcast field and a vector length field when the modifier field's content specifies memory access, wherein part of the beta field is interpreted as an RL field when the modifier field's content do not specify memory access;
distinguish, for each of the occurrences that specifies memory access through the modifier field's content, whether to perform a broadcast operation or not and which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the broadcast field and the vector length field in that occurrence; and
distinguish, for each of the occurrences that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that occurrence, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as the vector length field when the RL field's content indicates the vector length type operation;
distinguish, for each of the occurrences that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the beta field's content and its interpretation as the round operation field in that occurrence; and
distinguish, for each of the occurrences, whether to perform a merging write mask operation or a zeroing write mask operation based on the alpha field's content and its interpretation as a write mask control field in that occurrence.

2. The apparatus of claim 1 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero.

3. The apparatus of claim 1 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field specification of different data element widths.

4. The apparatus of claim 3 , wherein the different data element widths include 32 bits and 64 bits.

5. The apparatus of claim 1 , wherein the first instruction format also supports through different values in a real opcode field inside the base operation field the specification of an 8 bit and a 16 bit data element width.

6. The apparatus of claim 1 , wherein the first instruction format further includes a real opcode field inside the base operation field, wherein the real opcode field's content distinguishes whether the data element width field's content selects between a 64 bit and a 32 bit data element size or selects between a 16 bit and an 8 bit data element size for each of the occurrences.

7. The apparatus of claim 1 , wherein the plurality of vector lengths include 128 bits, 256 bits, and 512 bits.

8. The apparatus of claim 1 , wherein the broadcast operation includes 1-element granularity broadcast.

9. The apparatus of claim 1 , wherein at least certain of the different base operations operate on two source operands and a destination operand does not overwrite either of the two source operands.

10. The apparatus of claim 1 , wherein at least certain of the different base operations operate on two source operands and a destination operand overwrites one of the two source operands.

11. The apparatus of claim 1 , wherein the second class supports the modifier field's content specifying a memory access operation with a scaled displacement, in which case the first instruction format includes a displacement factor field and fields from which a scale, an index, and a base are pulled, wherein the scaled displacement is generated based on multiplying the size of a memory access by the displacement factor field's content, and wherein the scale, index, base, and scaled displacement are used to generate an address for the memory access.

12. The apparatus of claim 11 , wherein the address is generated by 2 scale +the index+the base+the scaled displacement.

13. The apparatus of claim 11 , wherein the displacement factor field's content is interpreted as a signed value between −128 and 127.

14. The apparatus of claim 11 , wherein the supported sizes of the memory access are 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, and 64 bytes.

15. An apparatus comprising:
an instruction converter to convert an instruction from a first instruction set to one or more instructions of a different second instruction set, wherein the first instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, an alpha field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, and the beta field on each occurrence of an instruction in the first instruction format in instruction streams, the instruction converter to determine the occurrences of the instructions in the first instruction format for translation as follows:
distinguish the occurrences of instructions in the first instruction format that specify memory access from those that do not based on the modifier field's content in those different occurrences, wherein the beta field is interpreted as a broadcast field and a vector length field when the modifier field's content specifies memory access, wherein part of the beta field is interpreted as an RL field when the modifier field's content do not specify memory access;
distinguish, for each of the occurrences that specifies memory access through the modifier field's content, whether to perform a broadcast operation or not and which one of a plurality of vector lengths to use based on the beta field's content and its interpretation as the broadcast field and the vector length field in that occurrence; and
distinguish, for each of the occurrences that does not specify memory access through the modifier field'

Assignees

• Intel Corp

Inventors

• Valentine Robert C
• San Adrian Jesus Corbal
• Sans Roger Espasa
• Cavin Robert D
• Toll Bret L
• Duran Santiago Galan
• Wiedemeier Jeffrey G
• Samudrala Sridhar
• Girkar Milind Baburao
• Grochowski Edward Thomas
• Hall Jonathan Cannon
• Bradford Dennis R
• Ould-Ahmed-Vall Elmoustapha
• Abel James C
• Charney Mark
• Abraham Seth
• Sair Suleyman
• Forsyth Andrew Thomas
• Wu Lisa
• Yount Charles

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D48/30

  Devices controlled by electric currents or voltages · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title