Multi-device asynchronous timing exchange for redundant clock synchronization

Patent metadata

Field	Value
Publication number	US-11209858-B2
Application number	US-201916522151-A
Country	US
Kind code	B2
Filing date	Jul 25, 2019
Priority date	Sep 26, 2018
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

First claim

What is claimed is:

1. A computing system comprising:
an oscillator configured to provide an oscillating signal;
a counter coupled to the oscillator and configured to maintain a running total of cycles of the oscillating signal, the running total of cycles being a system clock;
a communications interface configured to send and receive information; and
a processor configured to communicate with at least two other computing systems, determine a first time differential with respect to a first of the at least two other computing systems, and communicate the first time differential to another of the at least two other computing systems,
wherein the processor is further configured to receive a second time differential from the first of the at least two other computing systems, the second time differential being a time differential between the first of the at least two other computing systems and a second of the at least two other computing systems, and maintain a memory of time differentials from which an offset value between the at least two other computing systems may be determined.

2. The computing system of claim 1 , A computing system comprising:
an oscillator configured to provide an oscillating signal;
a counter coupled to the oscillator and configured to maintain a running total of cycles of the oscillating signal, the running total of cycles being a system clock;
a communications interface configured to send and receive information; and
a processor configured to communicate with at least two other computing systems, determine a first time differential with respect to a first of the at least two other computing systems, and communicate the first time differential to another of the at least two other computing systems,
wherein the processor is further configured to maintain a synchronized clock with a selected one of the at least two other computing systems, monitor for a failure criterion with respect to the selected computing system, and re-synchronize the synchronized clock with an alternate one of the at least two other computing systems upon detecting the failure criterion.

3. The computing system of claim 2 , wherein the processor is further configured to maintain the synchronized clock based upon the system clock and a first offset value derived from time differentials with respect to the selected computing system, and upon detecting the failure criterion to replace the first offset value with a second offset value derived from time differentials with respect to the alternate computing system.

4. The computing system of claim 3 , wherein the processor is further configured to derive the first offset value based upon a first time differential to the selected computing system and a second time differential from the selected computing system.

5. The computing system of claim 4 , wherein the processor is further configured to derive the first offset value as an average of the first time differential and the second time differential.

6. The computing system of claim 3 , wherein the processor is further configured to maintain derived values of the first offset value and the second offset value simultaneously.

7. The computing system of claim 3 , wherein the failure criterion is based upon the first offset value.

8. A computing system comprising:
an oscillator configured to provide an oscillating signal;
a counter coupled to the oscillator and configured to maintain a running total of cycles of the oscillating signal, the running total of cycles being a system clock;
a communications interface configured to send and receive information; and
a processor configured to communicate with at least two other computing systems, determine a first time differential with respect to a first of the at least two other computing systems, and communicate the first time differential to another of the at least two other computing systems,
wherein the processor is further configured to determine whether any of the system clock of the computing system or system clocks of the at least two other computing systems is stable, based upon offset values between various of the computing systems.

9. The computing system of claim 8 , wherein the processor is further configured to establish the stable system clock as a leader clock and to maintain a synchronized clock based upon the system clock and an offset to the leader clock.

10. The computing system of claim 8 , wherein the processor is further configured to determine whether any of the system clocks is failing, based upon offset values between various of the computing systems, and to eliminate the failing clock's eligibility to be a leader clock.

11. A method of operating a computer system comprising:
communicating with at least two other computing systems;
determining a first time differential with respect to a first of the at least two other computing systems;
communicating the first time differential to another of the at least two other computing systems;
receiving a second time differential from the first of the at least two other computing systems, the second time differential being a time differential between the first of the at least two other computing systems and a second of the at least two other computing systems; and
maintaining a memory of time differentials from which an offset value between the at least two other computing systems may be determined.

12. A method of operating a computer system comprising:
communicating with at least two other computing systems;
determining a first time differential with respect to a first of the at least two other computing systems;
communicating the first time differential to another of the at least two other computing systems;
maintaining a synchronized clock with a selected one of the at least two other computing systems;
monitoring for a failure criterion with respect to the selected computing system; and
re-synchronizing the synchronized clock with an alternate one of the at least two other computing systems upon detecting the failure criterion.

13. The method of claim 12 , further comprising:
maintaining the synchronized clock based upon the system clock and a first offset value derived from time differentials with respect to the selected computing system; and
replacing the first offset value with a second offset value derived from time differentials with respect to the alternate computing system responsive to detecting the failure criterion.

14. The method of claim 13 , further comprising deriving the first offset value based upon a first time differential to the selected computing system and a second time differential from the selected computing system.

15. The method of claim 14 , further comprising deriving the first offset value as an average of the first time differential and the second time differential.

16. The method of claim 13 , further comprising maintaining derived values of the first offset value and the second offset value simultaneously.

17. A method of operating a computing system comprising:
communicating with at least two other computing systems;
determining a first time differential with respect to a first of the at least two other computing systems;
communicating the first time differential to another of the at least two other computing systems; and
determining whether any of the system clock of the computing system or system clocks of the at least two other computing systems is stable, based upon offset values between various of the computing systems.

18. A redundant computing system comprising:
a plurality of compu

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Mautner Eric Karl
• Klingensmith Brianna

Classifications

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• G06F13/122 Primary

  where hardware performs an I/O function other than control of data transfer · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title