Electronic device capable of appropriately using various time displays

US11209781B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11209781-B2
Application numberUS-201916355529-A
CountryUS
Kind codeB2
Filing dateMar 15, 2019
Priority dateMar 23, 2016
Publication dateDec 28, 2021
Grant dateDec 28, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes first and second processors, and first and second display units. While the first and second processors cooperate with each other and perform a display operation including a time display, the first processor can be set to a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, or a pause mode in which a power consumption is lower than the power consumption in the low power mode, and the first processor is stopped. In the normal or low power modes, the first processor controls such that the first display unit displays a time, and the second processor controls such that the second display unit does not display a time. In the pause mode, the first display unit is turned off, and the second processor controls such that the second display unit displays a time.

First claim

Opening claim text (preview).

The invention claimed is: 1. An electronic device comprising: a first processor; a second processor; a first display unit; a second display unit; a first clock unit configured to count a time by control of the first processor; and a second clock unit configured to count a time separately from the first clock unit; wherein: the first processor and the second processor cooperate with each other and perform a display operation including a time display, the first processor can be selectively set to any of a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, and a pause mode in which a power consumption is lower than the power consumption in the low power mode, and the first processor is stopped, in the normal mode or the low power mode, the first processor controls such that the first display unit displays a time counted by the first clock unit, and the second processor controls such that the second display unit does not display a time, in the pause mode, the first display unit is turned off, and the second processor controls such that the second display unit displays a time counted by the second clock unit, and the first processor is configured to acquire time information from a first external source outside of the electronic device, and, in a case in which acquisition of the time information from the first external source fails, acquire the time information from a second external source outside of the electronic device, the second external source being different from the first external source, and correct a time counted by the first clock unit and the second clock unit based on the time information acquired from the first external source or from the second external source. 2. The electronic device according to claim 1 , wherein the second processor operates with at least one of a low power consumption and a low operation frequency in comparison with the first processor. 3. The electronic device according to claim 1 , wherein the second processor selectively sets a second normal mode in which the second processor normally operates the second processor, and a second low power mode in which the second processor operates with a low power consumption in comparison with the second normal mode. 4. The electronic device according to claim 2 , wherein the second processor selectively sets a second normal mode in which the second processor normally operates the second processor, and a second low power mode in which the second processor operates with a low power consumption in comparison with the second normal mode. 5. The electronic device according to claim 1 , wherein the second display unit is stacked on an upper portion of the first display unit, and in a state in which the second display unit does not display a time, the second display unit is controlled so as to transmit a display content of the first display unit. 6. The electronic device according to claim 2 , wherein the second display unit is stacked on an upper portion of the first display unit, and in a state in which the second display unit does not display a time, the second display unit is controlled so as to transmit a display content of the first display unit. 7. The electronic device according to claim 3 , wherein the second display unit is stacked on an upper portion of the first display unit, and in a state in which the second display unit does not display a time, the second display unit is controlled so as to transmit a display content of the first display unit. 8. The electronic device according to claim 4 , wherein the second display unit is stacked on an upper portion of the first display unit, and in a state in which the second display unit does not display a time, the second display unit is controlled so as to transmit a display content of the first display unit. 9. A display control method for an electronic device, the electronic device including a first processor, a second processor, a first display unit, a second display unit, a first clock unit configured to count a time by control of the first processor, and a second clock unit configured to count a time separately from the first clock unit, the method comprising: performing a display operation including a time display under cooperative control by the first processor and the second processor; selectively setting the first processor to any of a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, and a pause mode in which a power consumption is lower than a power consumption in the low power mode, and the first processor is stopped, in the normal mode or the low power mode, performing control by the first processor such that the first display unit displays a time counted by the first clock unit, and performing control by the second processor such that the second display unit does not display a time, in the pause mode, performing control such that the first display unit is turned off, and performing control by the second processor such that the second display unit displays a time counted by the second clock unit, acquiring, by the first processor, time information from a first external source outside of the electronic device, and, in a case in which acquisition of the time information from the first external source fails, acquiring, by the first processor, the time information from a second external source outside of the electronic device, the second external source being different from the first external source, and correcting, by the first processor, a time counted by the first clock unit and the second clock unit based on the time information acquired from the first external source or from the second external source. 10. The electronic device according to the claim 1 , wherein: the first external source is a wireless communication device; and the second external source is GPS satellite.

Assignees

Inventors

Classifications

  • G06F1/3265Primary

    Power saving in display device · CPC title

  • Visual time or date indication means · CPC title

  • Wearable computers, e.g. on a belt · CPC title

  • Details related to the display arrangement, including those related to the mounting of the display in the housing · CPC title

  • Power management, e.g. power saving · CPC title

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What does patent US11209781B2 cover?
An electronic device includes first and second processors, and first and second display units. While the first and second processors cooperate with each other and perform a display operation including a time display, the first processor can be set to a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, or a pause mode in which a powe…
Who is the assignee on this patent?
Casio Computer Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F1/3265. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 28 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).