Display substrate and manufacturing method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-11209709-B2
Application number	US-201716068297-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	May 10, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A display substrate and a method thereof, a display panel and a display device are provided. The display substrate includes: a base substrate; and at least one first signal line and a first insulating layer which are disposed on the base substrate; a surface of the first insulating layer away from the base substrate and a surface of the at least one first signal line away from the base substrate are parallel with the base substrate and are substantially located in a continuous flat plane. The first insulating layer which is disposed side by side with the first signal line can improve the surface flatness level of the display substrate and prevent the subsequently formed structures on the display substrate suffering from display defectives due to a too large step.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate; and
at least one first signal line and a first insulating layer, which are disposed on the base substrate, wherein the at least one first signal line is a common electrode line and the first insulating layer is a gate insulating layer,
wherein a surface of the first insulating layer away from the base substrate and a surface of the at least one first signal line away from the base substrate are parallel with the base substrate and are substantially located in a continuous flat plane.

2. The display substrate according to claim 1 , further comprising:
a second insulating layer disposed on the base substrate,
wherein the second insulating layer covers the first signal line and the first insulating layer.

3. The display substrate according to claim 2 , further comprising a first electrode or a semiconductor layer which is disposed on a side of the second insulating layer away from the base substrate.

4. The display substrate according to claim 1 , wherein the display substrate is an array substrate.

5. A display panel, comprising the display substrate according to claim 1 .

6. A display device, comprising the display panel according to claim 5 .

7. The display substrate according to claim 2 , wherein the display substrate is an array substrate.

8. A manufacturing method of a display substrate, comprising:
providing a base substrate;
forming at least one first signal line on the base substrate; and
forming a first insulating layer on the base substrate and the first insulating layer is disposed side by side with the at least one first signal line, wherein the at least one first signal line is a common electrode line and the first insulating layer is a gate insulating layer,
wherein a surface of the first insulating layer away from the base substrate and a surface of the at least one first signal line away from the base substrate are parallel with the base substrate and are substantially located in a continuous flat plane.

9. The manufacturing method according to claim 8 , wherein forming the at least one first signal line on the base substrate comprises:
providing a first mask;
depositing a conductive layer film on the base substrate and coating a first photoresist layer on the conductive layer film; and
exposing the first photoresist layer with the first mask, developing the exposed first photoresist layer to obtain a first photoresist pattern, and patterning the conductive layer film with the first photoresist pattern so as to form the at least one first signal line.

10. The manufacturing method according to claim 9 , wherein forming the first insulating layer on the base substrate and side by side with the at least one first signal line comprises:
in a direction perpendicular to the base substrate, depositing a first insulating layer film on the base substrate formed with the at least one first signal line, wherein a thickness of the first insulating layer film is substantially same as a thickness of the at least one first signal line;
coating a second photoresist layer on the first insulating layer film; and
on a side of the second photoresist layer away from the base substrate, exposing the second photoresist layer with the first mask, developing the exposed second photoresist layer to obtain a second photoresist pattern, and patterning the first insulating layer film with the second photoresist pattern so as to form the first insulating layer.

11. The manufacturing method according to claim 10 , wherein
the first photoresist layer is a positive photoresist layer and the second photoresist layer is a negative photoresist layer; or
the first photoresist layer is a negative photoresist layer and the second photoresist layer is a positive photoresist layer.

12. The manufacturing method according to claim 9 , wherein forming the first insulating layer on the base substrate and side by side with the at least one first signal line comprises:
in a direction perpendicular to the base substrate, depositing a first bate insulating layer film on the base substrate formed with the at least one first signal line, wherein a thickness of the first insulating layer film is substantially same as a thickness of the at least one first signal line;
forming a third photoresist layer on the first gate insulating layer film; and
on a side of the base substrate away from the at least one signal line, exposing the third photoresist layer by using the at least one signal line as a mask, developing the exposed third photoresist layer to obtain a third photoresist pattern, and patterning the first insulating layer film with the third photoresist pattern so as to form the first insulating layer.

13. The manufacturing method according to claim 12 , wherein
the third photoresist layer is a negative photoresist layer.

14. The manufacturing method according to claim 8 , further comprising:
forming a second insulating layer on the base substrate which is formed with the at least one first signal first line and the first insulating layer,
wherein the second insulating layer covers the at least one first signal line and the first insulating layer.

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Cui Xiaochen
• Li Peng
• Park Jungho
• Kim Jaikwang
• Li Zhe
• Li Xiaoji
• Zhao Dongxing

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title