Print head and liquid ejecting apparatus

Patent metadata

Field	Value
Publication number	US-11207886-B2
Application number	US-202017032165-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 27, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A print head includes ejecting portions ejecting liquid by being supplied with a high voltage signal, a switch group switching between whether or not to supply the high voltage signal to the first ejecting portion group in accordance with a low voltage logic signal, a memory, a high voltage signal input terminal, and a low voltage logic signal input terminal, the print head having a first mode in which the print head executes reading processing of reading information stored in the memory and does not execute ejection control processing of controlling whether or not to supply the high voltage signal to the first ejecting portion group by switching the switch group in accordance with an input signal input from the low voltage logic signal input terminal and a second mode in which the print head does not execute the reading processing and executes the ejection control processing.

First claim

What is claimed is:

1. A print head assembled to a liquid ejecting apparatus ejecting liquid with respect to a medium, the print head comprising:
a first ejecting portion ejecting the liquid by being supplied with a high voltage signal changing in voltage value;
a second ejecting portion ejecting the liquid by being supplied with the high voltage signal;
a first ejecting portion group having a plurality of ejecting portions including the first ejecting portion and the second ejecting portion;
a first switch switching between whether or not to supply the high voltage signal to the first ejecting portion in accordance with a low voltage logic signal having a maximum voltage value lower than a maximum voltage value of the high voltage signal and changing in voltage value;
a second switch switching between whether or not to supply the high voltage signal to the second ejecting portion in accordance with the low voltage logic signal;
a switch group having a plurality of switches including the first switch and the second switch;
a memory;
a high voltage signal input terminal to which the high voltage signal is input; and
a low voltage logic signal input terminal to which the low voltage logic signal is input,
wherein the print head has:
a first mode in which the print head executes reading processing of reading information stored in the memory and does not execute ejection control processing of controlling whether or not to supply the high voltage signal to the first ejecting portion group by switching the switch group in accordance with an input signal input from the low voltage logic signal input terminal; and
a second mode in which the print head does not execute the reading processing and executes the ejection control processing in accordance with the input signal.

2. The print head according to claim 1 , wherein
the low voltage logic signal includes a first low voltage logic signal, a second low voltage logic signal, and a third low voltage logic signal,
the low voltage logic signal input terminal includes a first low voltage logic signal input terminal to which the first low voltage logic signal is input and including two states of an H-level state and an L-level state, a second low voltage logic signal input terminal to which the second low voltage logic signal is input and including two states of an H-level state and an L-level state, and a third low voltage logic signal input terminal to which the third low voltage logic signal is input and including two states of an H-level state and an L-level state,
a signal for causing the second low voltage logic signal input terminal to reach the H-level state is input, a signal for causing the third low voltage logic signal input terminal to reach the H-level state is input, and a signal for causing the first low voltage logic signal input terminal to change between the H-level state and the L-level state is input in the first mode, and
a signal for preventing the second low voltage logic signal input terminal and the third low voltage logic signal input terminal from simultaneously reaching the H-level state is input in the second mode.

3. The print head according to claim 2 , wherein a signal for executing the reading processing is input to the first low voltage logic signal input terminal in the first mode.

4. The print head according to claim 2 , wherein the first low voltage logic signal for switching between whether or not to supply the high voltage signal to the first ejecting portion group by switching the switch group is input in the second mode.

5. The print head according to claim 2 , wherein the second low voltage logic signal for defining an ejection timing when the liquid is ejected from the first ejecting portion group is input in the second mode.

6. The print head according to claim 2 , wherein
the high voltage signal includes a first voltage waveform and a second voltage waveform in accordance with the amount of the liquid ejected from the first ejecting portion group, and
the third low voltage logic signal for defining a timing of switching between the first voltage waveform and the second voltage waveform is input in the second mode.

7. The print head according to claim 1 , wherein the reading processing is executed after a power supply voltage is supplied and before the high voltage signal for ejecting the liquid from the first ejecting portion group is supplied to the first ejecting portion group.

8. The print head according to claim 1 , wherein the memory is a non-volatile memory.

9. The print head according to claim 8 , wherein the non-volatile memory is a One Time PROM.

10. The print head according to claim 8 , wherein the non-volatile memory is an EPROM.

11. A liquid ejecting apparatus comprising:
a drive signal output circuit outputting a drive signal; and
a print head assembled to the liquid ejecting apparatus ejecting liquid with respect to a medium, wherein
the print head assembled to the liquid ejecting apparatus ejecting the liquid with respect to the medium includes:
a first ejecting portion ejecting the liquid by being supplied with a high voltage signal changing in voltage value;
a second ejecting portion ejecting the liquid by being supplied with the high voltage signal;
a first ejecting portion group having a plurality of ejecting portions including the first ejecting portion and the second ejecting portion;
a first switch switching between whether or not to supply the high voltage signal to the first ejecting portion in accordance with a low voltage logic signal having a maximum voltage value lower than a maximum voltage value of the high voltage signal and changing in voltage value;
a second switch switching between whether or not to supply the high voltage signal to the second ejecting portion in accordance with the low voltage logic signal;
a switch group having a plurality of switches including the first switch and the second switch;
a memory;
a high voltage signal input terminal to which the high voltage signal is input; and
a low voltage logic signal input terminal to which the low voltage logic signal is input, and
the print head has:
a first mode in which the print head executes reading processing of reading information stored in the memory and does not execute ejection control processing of controlling whether or not to supply the high voltage signal to the first ejecting portion group by switching the switch group in accordance with an input signal input from the low voltage logic signal input terminal, and
a second mode in which the print head does not execute the reading processing and executes the ejection control processing in accordance with the input signal.

12. The liquid ejecting apparatus according to claim 11 , wherein
the low voltage logic signal includes a first low voltage logic signal, a second low voltage logic signal, and a third low voltage logic signal,
the low voltage logic signal input terminal includes a first low voltage logic signal input terminal to which the first low voltage logic signal is input and including two states of an H-level state and an L-level state, a second low voltage logic signal input terminal to which the second low voltage logic signal is input and including two states of an H-level state and an L-level state, and a third low voltage logic signal input terminal to which the third low voltage logic signal is input and including two states of an H-level state and an L-level state,
a signal for causing the second low voltage logic signal input terminal to reach the H-level state is input, a signal for causing the third low voltage logic signal input terminal to reach the H-level state is input, and a sign

Assignees

• Seiko Epson Corp

Inventors

• Takagi Eiji
• Koizumi Masanori
• Komatsu Shunya
• Nakano Shuichi
• Kamiyanagi Masashi
• Matsuyama Toru

Classifications

• B41J2/04545

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• B41J2/01 Primary

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• B41J2/04501

  Control methods or devices therefor, e.g. driver circuits, control circuits · CPC title

• B41J2/04548

  Details of power line section of control circuit · CPC title

• B41J2/04581

  controlling heads based on piezoelectric elements · CPC title