Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver

Patent metadata

Field	Value
Publication number	US-11206163-B2
Application number	US-202117205960-A
Country	US
Kind code	B2
Filing date	Mar 18, 2021
Priority date	Nov 10, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.

First claim

The invention claimed is:

1. A time-to-digital converter-based hybrid polar data converter (converter) for a polar receiver, comprising:
a time-to-digital converter (TDC) with a reconfigurable temporal resolution and a variable number of bits input, wherein the TDC detects phase information of a received signal;
an analog-to-digital converter (ADC), wherein the ADC detects an amplitude information of the received signal;
a first tunable temporal delay cell configured in an ADC path and a plural path of fixed temporal delay cells located in the ADC path, wherein the first tunable temporal delay cell is controlled by the TDC's output to precisely set the ADC sample position at a maximum of a symbol period; and
a digital domain one cycle delay coupled to the output of the TDC to align the TDC's output with the ADC's output.

2. The converter of claim 1 further comprising a hysteresis buffer copied to an input of the TDC, wherein the hysteresis buffer eliminates signal amplitude information.

3. The converter of claim 1 further comprising a clock synthesis module with a multi-phase output, wherein the module is controlled by a feedback signal, the feedback signal is used to synchronize a local clock phase with the received signal.

4. The converter of claim 3 further comprising a multiphase selection multiplexer coupled to an output of the baseband clock synthesis module, wherein the multiplexer is controlled by the digital baseband and selects a closest phase generated by the synthesis module for an approximate local clock synchronization.

5. The converter of claim 4 further comprising a second tunable temporal delay cell coupled to an output of the multi-phase selection multiplexer, wherein the second tunable temporal delay cell further controls the local clock phase for fine local clock synchronization.

6. The converter of claim 1 , wherein the received signal is a modulated signal on an RF signal.

7. The converter of claim 1 , wherein an ADC sampling position for detecting the amplitude information is determined by the received phase information.

8. The converter of claim 1 , such that the outputs include digitalized phase and amplitude data.

9. The converter of claim 1 , wherein the first tunable temporal delay cell is controlled by the output of the TDC to precisely set the ADC sample position at a maximum of a symbol period.

10. A polar analog-to-digital conversion method utilizing a time-to-digital based hybrid polar data converter (converter), comprising:
approximately aligning a local clock phase by selecting a closest phase generated from a multi-phase local clock synthesis block;
finely aligning a local clock phase by adjusting a tunable temporal delay cell for the fine alignment; adjusting a tunable delay in an analog-to-digital converter (ADC) path based on an upper and lower threshold value settings of a hysteresis buffer;
detecting a time from a local clock rising edge using a time-to-digital converter (TDC) block obtained in the aligning steps to a rising zero-crossing point and a falling zero-crossing point of a received signal, and converting the time interval information into corresponding digital codes;
adjusting an ADC sample position by adjusting the tunable delay based on an output of the TDC and selecting one signal delay path based on a position of the received signal's rising and falling zero-crossing points.

11. The conversion method according to claim 10 , comprising:
adjusting a sampling clock of the ADC to the desired sampling position based on the TDC's output with a tunable temporal delay cell.

12. The conversion method according to claim 11 , further comprising selecting with a multiplexer one of two signals passing through two delay paths based on a choice of rising or falling zero-crossing point, wherein the two paths of signal delay are in the ADC path, one including a one and ¼ cycle temporal delay corresponding to the falling zero crossing point detection of the TDC, and the other one including ¾ cycle temporal delay corresponding to the rising zero-crossing point detection of the TDC.

13. The conversion method according to claim 12 further comparing, calculating a compensation gain based on the ADC sample position in a symbol period and the pulse shape filter profile parameters to restore the nonfiltered signal with time domain signal processing.

14. A time-to-digital converter-based hybrid polar data converter (converter) for a polar receiver, comprising:
a time-to-digital converter (TDC) with a reconfigurable temporal resolution and a variable number of control bits input, wherein the TDC detects a phase information of a received signal, wherein the received signal is an analog signal on an RF signal;
an analog-to-digital converter (ADC), wherein the ADC detects an amplitude information of the received signal, wherein an ADC sampling position for detecting the amplitude information is determined by the received phase information;
a hysteresis buffer copied to an input of the TDC, wherein the hysteresis buffer eliminates signal amplitude information;
a baseband clock synthesis module with a multi-phase output, wherein the module is controlled by a feedback signal, the feedback signal received from a digital baseband and the feedback signal is used to synchronize a local clock phase with the received signal;
a multi-phase selection multiplexer coupled to an output of the clock synthesis module, wherein the multiplexer selects a closest phase generated by the synthesis module for an approximate local clock synchronization;
a first tunable temporal delay cell configured in an ADC path and a plural path of fixed temporal delay cells located in the ADC path, wherein the first tunable temporal delay cell is controlled by the TDC's output to precisely set the ADC sample position at a maximum of a symbol period;
a second tunable temporal delay cell coupled to an output of the multi-phase selection multiplexer, wherein the second tunable temporal delay cell further controls the local clock phase for fine local clock synchronization;
and a digital domain one cycle delay coupled to the output of the TDC to align the TDC's output with the ADC's output, such that the outputs include digitalized phase and amplitude data.

Assignees

• Univ Auburn

Inventors

• Dai Fa
• Wang Hechen

Classifications

• H03D3/006 Primary

  by sampling the oscillations and further processing the samples, e.g. by computing techniques (H03D3/007 takes precedence) · CPC title

• H04L27/22 Primary

  Demodulator circuits; Receiver circuits · CPC title

• H03D7/165

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

• H04B1/00

  Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title