Grid array connector system

Patent metadata

Field	Value
Publication number	US-11205867-B2
Application number	US-202016784270-A
Country	US
Kind code	B2
Filing date	Feb 7, 2020
Priority date	Sep 15, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A grid array connector system is provided that includes cables that are mounted on a board which has a chip packaged mounted thereon. The cables include conductors that are connected to support vias positioned in openings in the board and the conductors are connected to the support vias. The board can be connected to a second board which provides a stiffening ring. The board can be connected to the second board by deflectable terminals which are press-fit into the second board.

First claim

We claim:

1. A compute system comprising:
a lower circuit board; and
an upper circuit board having a top surface with a chip package mounted thereon, and a plurality of connecting passages therethrough outwardly of the chip package, the connecting passages extending from the top surface, the upper circuit board being mounted on the lower circuit board, wherein the upper circuit board only partially overlaps the lower circuit board such that a portion of the lower circuit board extends outwardly from edges of the upper circuit board and forms a stiffening ring surrounding the upper circuit board.

2. The compute system of claim 1 , further comprising a plurality of upper grid array connector systems mounted on the upper circuit board, each upper grid array connector system including cables supported by a housing and which are connected to the connecting passages on the upper circuit board.

3. The compute system of claim 2 , further comprising:
a compression member including a base having compression fingers extending therefrom and latch aims extending therefrom, the latch aims engaging latch catches on the housings; and
a heat sink engaged with the compression fingers and the chip package.

4. The compute system of claim 3 , wherein the compression member is formed of a single base which engages all of the housings of the plurality of upper grid array connector systems.

5. The compute system of claim 4 , wherein the upper grid array connector systems form a passageway in which the chip package is seated, and wherein the compression member has a cutout which aligns with the passageway, the heat sink having a projection which extends through the passageway and through the cutout.

6. The compute system of claim 5 , further comprising a plurality of lower grid array connector systems mounted on the lower circuit board, each lower grid array connector system including cables supported by a housing.

7. The compute system of claim 6 , further comprising:
a compression member including a base having compression fingers extending therefrom and latch arms extending therefrom, the latch arms engaging latch catches on the housings of the plurality of lower grid array connector systems; and
a lower retaining frame attached to the heat sink and engaged with the compression fingers.

8. The compute system of claim 1 , further comprising a plurality of lower grid array connector systems mounted on the lower circuit board, each lower grid array connector system including cables supported by a housing.

9. The compute system of claim 8 , further comprising:
a compression member including a base having compression fingers extending therefrom and latch arms extending therefrom, the latch arms engaging latch catches on the housings of the plurality of lower grid array connector systems; and
a lower retaining frame attached to the heat sink and engaged with the compression fingers.

10. The compute system of claim 8 , further comprising retaining legs connecting the lower retaining frame and the heat sink together, the retaining legs passing through the stiffening ring.

11. A compute system for mounting a chip package, comprising:
a first circuit board with a mounting surface and a connecting surface opposite the mounting surface, the first circuit board having a first array of pads on the mounting surface, the first array of pads being in communication with the chip package, the first circuit board further including a plurality of support vias extending from the mounting surface to the connecting surface and signal pads on the connecting surface in communication with the respective support vias;
a grid array connector system positioned on a side of the chip package, the grid array connector system including a plurality of cables, each cable including a pair of conductors, wherein each of the conductors is electrically connected to one of the support vias;
a second circuit board with a mounting surface and a connecting surface opposite the mounting surface and a plurality of support vias extending from the mounting surface of the second circuit board to the connecting surface of the second circuit board; and
a terminal positioned within each support via of the second circuit board and extending outwardly from the mounting surface thereof, each terminal including a press-fit portion which is press-fit into the respective support via of the second circuit board and electrically connected thereto and a deflectable portion extending from the press-fit portion and outwardly from the mounting surface of the second circuit board,
wherein when the first and second circuit boards are mated together, the deflectable portion engages with the signal pad of the first circuit board.

12. The compute system of claim 11 , wherein each deflectable portion has a bent back arm having a hooked end, wherein a free end of the hooked end faces the mounting surface of the second circuit board.

13. The compute system of claim 12 , wherein each press-fit portion includes a deformable body which deforms when the press-fit portion is press-fit into the respective support via in the second circuit board.

14. The compute system of claim 13 , wherein each support vias in the second circuit board into which the press-fit portion is inserted is cylindrical.

15. The compute system of claim 11 , wherein each press-fit portion includes a deformable body which deforms when the press-fit portion is press-fit into the respective support via in the second circuit board.

16. The compute system of claim 11 , further comprising a solder charge in communication with each support via of the second circuit board.

17. The compute system of claim 11 , further comprising:
a plurality of first pedestals mounted on the mounting surface of the first circuit board;
a plurality of second pedestals electrically connected to the first pedestals; and
a housing positioned on the first circuit board and at least partially covering the plurality of first and second pedestals.

18. The compute system of claim 11 , further comprising a heat sink mounted on the first circuit board.

Assignees

• Molex Llc

Inventors

• Lloyd Brian Keith
• Walz Gregory
• Waggener Colby
• Hille Karen
• Reed Bruce
• Dalvi Sagar
• Tsai Chitaou

Classifications

• H10W40/226

  characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461) · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title