1S1R memory integrated structure with larger selector surface area which can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11205750-B2
Application number	US-202016786346-A
Country	US
Kind code	B2
Filing date	Feb 10, 2020
Priority date	May 14, 2018
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

First claim

What is claimed is:

1. A 1S1R memory cell, comprising: a word line metal, a resistive material layer, a first selector electrode, a selector material layer, a second selector electrode, an interconnection wire, and a bit line metal;
wherein the selector material layer is in a shape of a groove, and the second selector electrode is formed in the groove,
wherein an area of the selector material layer is larger than an area of the resistive material layer, and
wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , and Y 2 O 3 ; and a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbOx, and VO 2 .

2. The 1S1R memory cell of claim 1 , further comprising a first memory electrode and a second memory electrode, wherein the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire.

3. The 1S1R memory cell of claim 1 , wherein the resistive material layer is on the word line metal or on the second selector electrode.

4. A method for fabricating a 1S1R memory cell, comprising:
forming sequentially, from bottom to top, a word line metal, a resistive material layer and a first selector electrode;
forming an insulating layer on the first selector electrode, etching the insulating layer to form a groove structure;
forming a groove-shaped selector material layer in the groove structure;
forming a second selector electrode in the groove of the selector material layer; and
forming sequentially an interconnection wire and a bit line metal on the second selector electrode,
wherein the 1S1R memory cell further comprises a first memory electrode and a second memory electrode, the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire; an area of the formed selector material layer is greater than an area of the resistive material layer, and
wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , and Y 2 O 3 ; a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbOx, and VO 2 ; and a material of the insulating layer comprises SiO 2 .

5. The method for fabricating the 1S1R memory cell of claim 4 , wherein in the etching of the insulating layer, the insulating layer is etched to an upper surface of the interconnection wire, and thus a bottom surface of the groove structure is flush with the upper surface of the interconnection wire.

6. A method for fabricating a 1S1R memory cell, comprising:
forming sequentially, from bottom to top, a word line metal and a first selector electrode;
forming an insulating layer on the first selector electrode, etching the insulating layer to form a groove structure;
forming a groove-shaped selector material layer in the groove structure;
forming a second selector electrode in the groove of the selector material layer; and
forming sequentially a resistive material layer, an interconnection wire and a bit line metal on the second selector electrode,
wherein the 1S1R memory cell further comprises a first memory electrode and a second memory electrode, the word line metal is also used as the first memory electrode of the 1S1R memory cell, and the first selector electrode is also used as the second memory electrode of the 1S1R memory cell and an interconnection wire; an area of the formed selector material layer is greater than an area of the resistive material layer, and
wherein the word line, the bit line, the interconnection wire, the resistive material layer, and the selector material layer are formed by a process of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering; a material of the word line, the bit line and the interconnection wire comprises W or Cu; a thickness of the resistive material layer is between 5 nm and 60 nm, and a material of the resistive material layer comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , and Y 2 O 3 ; a thickness of the selector material layer is between 5 nm and 60 nm, and a material of the selector material layer comprises a metal oxide or a mixed ion-electron conducting (MIEC) material; the metal oxide comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbOx, and VO 2 ; and a material of the insulating layer comprises SiO 2 .

7. The method for fabricating the 1S1R memory cell of claim 6 , wherein in the etching of the insulating layer, the insulating layer is etched to an upper surface of the interconnection wire, and thus a bottom surface of the groove structure is flush with the upper surface of the interconnection wire.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Luo Qing
• Lv Hangbing
• Liu Ming
• Xu Xiaoxin
• Lu Cheng

Classifications

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• H01L45/16

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic