Method of preparing thin film transistor substrate

Patent metadata

Field	Value
Publication number	US-11205667-B2
Application number	US-201916642949-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	May 24, 2018
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

Disclosed is a method of preparing a thin film transistor substrate, a thin film transistor substrate, and a display apparatus. The method includes forming a conductive material layer, forming a hydrophobic insulation layer on the conductive material layer, forming a photoresist layer on the hydrophobic insulation layer, patterning the photoresist layer to form a photoresist pattern, removing a segment in the hydrophobic insulation layer that is not covered by the photoresist pattern to form a hydrophobic insulation pattern, and removing a segment in the conductive material layer that is not covered by the hydrophobic insulation pattern to form a conductive pattern.

First claim

What is claimed is:

1. A method of preparing a thin film transistor substrate, comprising:
forming a conductive material layer, wherein the conductive material layer comprises two diffusion prevention layers and a copper layer between the two diffusion prevention layers,
forming a hydrophobic insulation layer on the conductive material layer,
forming a photoresist layer on the hydrophobic insulation layer,
patterning the photoresist layer to form a photoresist pattern,
removing a segment in the hydrophobic insulation layer that is not covered by the photoresist pattern to form a hydrophobic insulation pattern, and
removing a segment in the conductive material layer that is not covered by the hydrophobic insulation pattern to form a conductive pattern.

2. The method of claim 1 , wherein the conductive material layer comprises a source-drain material layer, and the conductive pattern comprises a source electrode and a drain electrode.

3. The method of claim 1 , wherein a material of one of the two diffusion prevention layers comprises a metal, a metal nitride, or a metal alloy.

4. The method of claim 1 , wherein a material of the hydrophobic insulation layer comprises a silicon nitride.

5. The method of claim 1 , further comprising, prior to forming the conductive material layer:
forming a gate electrode,
forming a gate insulation layer on the gate electrode, and
forming an active layer on the gate insulation layer;
and forming the conductive material layer comprises:
forming the conductive material layer on the active layer.

6. The method of claim 1 , further comprising, subsequent to removing the segment in the conductive material layer that is not covered by the hydrophobic insulation pattern to form the conductive pattern:
forming an active layer on the conductive pattern,
forming a gate insulation layer on the active layer, and
forming a gate electrode on the gate insulation layer.

7. The method of claim 1 , further comprising:
forming a via in the hydrophobic insulation pattern to expose a part of the conductive pattern.

8. The method of claim 7 , wherein patterning the photoresist layer to form the photoresist pattern comprises:
exposing the photoresist layer with a halftone mask, such that the photoresist layer is divided into a photoresist completely removed region, a photoresist partially reserved region and a photoresist completely reserved region, wherein an orthographic projection of a combination of the photoresist completely reserved region and the photoresist partially reserved region on the conductive material layer coincides with the conductive pattern, and
developing the photoresist layer, to completely remove a photoresist in the photoresist completely removed region, remove a part of a photoresist in the photoresist partially reserved region and reserve a remaining part of the photoresist in the photoresist partially reserved region and completely reserve a photoresist in the photoresist completely reserved region, wherein the photoresist pattern comprises the photoresist in the photoresist completely reserved region and the remaining part of the photoresist in the photoresist partially reserved region; and
forming the via in the hydrophobic insulation pattern to expose the part of the conductive pattern comprises:
completely removing the remaining part of the photoresist in the photoresist partially reserved region, to expose a part of the hydrophobic insulation pattern, and
removing the part of the hydrophobic insulation pattern, to expose the part of the conductive pattern.

9. The method of claim 8 , wherein completely removing the remaining part of the photoresist in the photoresist partially reserved region comprises:
performing an ashing treatment on the photoresist in the photoresist completely reserved region and the remaining part of the photoresist in the photoresist partially reserved region, to partially remove the photoresist in the photoresist completely reserved region and completely remove the remaining part of the photoresist in the photoresist partially reserved region.

10. The method of claim 8 , wherein completely removing the remaining part of the photoresist in the photoresist partially reserved region comprises:
exposing and developing the photoresist in the photoresist completely reserved region and the remaining part of the photoresist in the photoresist partially reserved region, to partially remove the photoresist in the photoresist completely reserved region and completely remove the remaining part of the photoresist in the photoresist partially reserved region.

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Gong Kui
• Xu Dezhi
• Tian Wei
• Gu Honggang
• Zhang Yuhu

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title