Memory devices for pattern matching

Patent metadata

Field	Value
Publication number	US-11205481-B2
Application number	US-202117218243-A
Country	US
Kind code	B2
Filing date	Mar 31, 2021
Priority date	Jan 12, 2015
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells comprising a plurality of memory cell pairs, wherein each memory cell pair of the plurality of memory cell pairs is configured to be programmed to store a same digit of data corresponding to a particular digit position of key words to be searched in the memory device; and
control circuitry for access of the array of memory cells;
wherein the control circuitry, when checking for a match of a stored digit of data of the plurality of memory cell pairs and a data value of the particular digit position of a received key word, is configured to cause the memory device to:
for each memory cell pair of the plurality of memory cell pairs:
apply a first voltage level to a control gate of a first memory cell of that memory cell pair;
apply a second voltage level, different than the first voltage level, to a control gate of a second memory cell of that memory cell pair; and
determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first voltage level to the control gate of the first memory cell of that memory cell pair and applying the second voltage level to the control gate of the second memory cell of that memory cell pair; and

deem a match condition to be met between the data value of the particular digit position of the received key word and the stored digit of data of the plurality of memory cell pairs when a number of the memory cell pairs of the plurality of memory cell pairs that are deemed to be deactivated is greater than or equal to a predetermined number of the memory cell pairs of the plurality of memory cell pairs that is less than a total number of memory cell pairs of the plurality of memory cell pairs.

2. The memory device of claim 1 , wherein the control circuitry is further configured to cause the memory device to deem a no-match condition between the data value of the particular digit position of the received key word and the stored digit of data of the plurality of memory cell pairs when the number of the memory cell pairs of the plurality of memory cell pairs that are deemed to be deactivated is less than the predetermined number.

3. The memory device of claim 1 , wherein the predetermined number is greater than the total number divided by two.

4. The memory device of claim 1 , wherein the control circuitry is further configured to cause the memory device to deem a match condition between the data value of the particular digit position of the received key word and the stored digit of data of the plurality of memory cell pairs when a majority of the memory cell pairs of the plurality of memory cell pairs are deemed to be deactivated.

5. The memory device of claim 1 , wherein the plurality of memory cell pairs comprises two memory cell pairs.

6. The memory device of claim 5 , wherein the plurality of memory cell pairs comprises three or more memory cell pairs.

7. The memory device of claim 1 , further comprising:
a plurality of data lines;
wherein each memory cell pair of the plurality of memory cell pairs is selectively connected to a respective data line of the plurality of data lines.

8. A memory device, comprising:
an array of memory cells comprising N strings of series-connected memory cells, wherein each string of series-connected memory cells of the N strings of series-connected memory cells comprises a respective set of memory cell pairs configured to be programmed to store a same pattern of data;
a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a first end of a respective string of series-connected memory cells of the N strings of series-connected memory cells; and
a source, wherein the source is selectively connected to a second end of each string of series-connected memory cells of the N strings of series-connected memory cells; and
control circuitry for access of the array of memory cells;
wherein the control circuitry, when checking for a match between a pattern of data of a received key word and a stored pattern of data of each respective set of memory cell pairs of the N strings of series-connected memory cells, is configured to cause the memory device to:
for each string of series-connected memory cells of the N strings of series-connected memory cells:
for each memory cell pair of the respective set of memory cell pairs of that string of series-connected memory cells:
biasing a control gate of a first memory cell of that memory cell pair to a first voltage level if a respective digit of the pattern of data of the received key word has a first data value, and biasing the control gate of the first memory cell of that memory cell pair to a second voltage level different than the first voltage level if the respective digit of the pattern of data of the received key word has a second data value different than the first data value;
biasing a control gate of a second memory cell of that memory cell pair to the second voltage level if the respective digit of the pattern of data of the received key word has the first data value, and biasing the control gate of the second memory cell of that memory cell pair to the first voltage level if the respective digit of the pattern of data of the received key word has the second data value;

determine whether that string of series-connected memory cells is deemed to be conducting or non-conducting between the source and its respective data line in response to biasing the control gates of the first memory cells and the second memory cells of each memory cell pair of the respective set of memory cell pairs of that string of series-connected memory cells; and

deem a match condition to be met between the pattern of data of the received key word and the stored pattern of data of each respective set of memory cell pairs of the N strings of series-connected memory cells when a number of the strings of series-connected memory cells of the N strings of series-connected memory cells that are deemed to be non-conducting is greater than or equal to K strings of series-connected memory cells of the N strings of series-connected memory cells, where K is less than N and greater than zero.

9. The memory device of claim 8 , wherein the array of memory cells further comprises additional strings of series-connected memory cells, wherein each string of series-connected memory cells of the additional strings of series-connected memory cells has a first end selectively connected to a respective data line of the plurality of data lines, and has a second end selectively connected to the source.

10. The memory device of claim 8 , wherein K is greater than N/2.

11. The memory device of claim 10 , wherein N is an odd integer value.

12. The memory device of claim 8 , wherein the N strings of series-connected memory cells is a first N strings of series-connected memory cells, wherein the array of memory cells further comprises a second N strings of series-connected memory cells, wherein each string of series-connected memory cells of the second N strings of series-connected memory cells comprises a respective set of memory cell pairs configured to be programmed to store a same pattern of data different than the pattern of data that the first N strings of series-connected memory cells is configured to be programmed to store, and wherein each string of series-connected memory cells of the additional strings of series-connected memory cells has a first end selectively connected to a respective data line of the plurality of data lines and has a second end selectively connected to the source.

13. The memory device of claim 12 , where

Assignees

• Micron Technology Inc

Inventors

• De Santis Luca
• Vali Tommaso
• Eldredge Kenneth J
• Sarin Vishal

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C15/046 Primary

  using non-volatile storage elements · CPC title