High resolution time capture circuit and corresponding device, capture method and computer program product

Patent metadata

Field	Value
Publication number	US-11204620-B2
Application number	US-202016851988-A
Country	US
Kind code	B2
Filing date	Apr 17, 2020
Priority date	Apr 26, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

First claim

What is claimed is:

1. A time capture circuit to measure time between events of a logic input signal, the time capture circuit comprising:
a delay line configured to receive the logic input signal and to generate a plurality of consecutive increasingly delayed replicas of the logic input signal, each replica delayed by a fixed delay with respect to a preceding replica;
a free running counter that is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor;
a counter value capture circuit coupled to receive a counter value from the free running counter and to also receive the logic input signal, the counter value capture circuit configured to capture the counter value upon occurrence of an event in the logic input signal outputting a captured counter value and to issue a trigger signal; and
a decoder coupled to the logic input signal, the plurality of consecutive increasingly delayed replicas, the captured counter value and the trigger signal, the decoder being configured to determine a decoded value based on values of the logic input signal and of the plurality of consecutive increasingly delayed replicas when the trigger signal is issued and to compute a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

2. The time capture circuit according to claim 1 , wherein the events comprise edges of the logic input signal.

3. The time capture circuit according to claim 1 , wherein the delay line comprises a number M of delay circuits, wherein M=2 N , N being a given integer size factor, and wherein the second scale factor is equal to the integer size factor N minus the first scale factor.

4. The time capture circuit according to claim 1 , further comprising a configuration register configured to supply the first scale factor to the counter value capture circuit and to the decoder and to supply the clock scale factor to the free running counter.

5. The time capture circuit according to claim 1 , wherein the decoder is configured to access a first decoding table comprising records that include, as fields, the values of an external signal and of other consecutive increasingly delayed replicas at a capture event corresponding to an external signal event, and the corresponding decoded value, which value corresponds with a capture interval in which the external signal event occurs.

6. The time capture circuit according to claim 5 , wherein the records are arranged in rows and the fields are arranged in columns.

7. The time capture circuit according to claim 1 , wherein the decoder is further configured to compare, periodically with a frequency of the counter clock signal, a current value of the logic input signal and a current value of each of the plurality of consecutive increasingly delayed replicas at a current clock period with a previous value of the logic input signal and a previous value of each of the plurality of consecutive increasingly delayed replicas at a previous clock period to identify value changes.

8. The time capture circuit according to claim 7 wherein the decoder is configured to issue a feedback trigger signal to the counter value capture circuit to store the counter value in response to a change in value of at least one of the logic input signal or one of the plurality of consecutive increasingly delayed replicas, unless a current value of the logic input signal and a current value of each of the plurality of consecutive increasingly delayed replicas at a current clock period are all zeros or all ones.

9. The time capture circuit according to claim 8 , wherein the decoder is configured to access a first decoding table comprising records that include, as fields, the values of an external signal and of other consecutive increasingly delayed replicas at a capture event corresponding to an external signal event, and the corresponding decoded value, which value corresponds with a capture interval in which the external signal event occurs.

10. The time capture circuit according to claim 9 , wherein the decoder is configured to access an enhanced decoder table that includes a further field indicating the result of the comparison with respect to the external signal and a further field indicating a capture length value.

11. The time capture circuit according to claim 10 , wherein the enhanced decoder table associates records corresponding to the first decoder table to a conventional value of capture length and to a positive result of the comparison for the external signal, and sets of records associated to a negative result of the comparison for the external signal and to respective different values of capture length storing in each record the values taken by the external signal and delayed replicas at the capture event when the event occurs in one of the capture intervals.

12. A method for time capture to measure time between event edges of a logic input signal, the method comprising:
inputting, to a delay line, the logic input signal to generate a plurality of consecutive increasingly delayed replicas of the logic input signal, each replica delayed by a fixed delay with respect to a preceding replica;
operating a free running counter clocked by counter clock signal corresponding to an external clock signal multiplied by a clock scale factor and an supplying a counter value to a counter value capture circuit capturing the counter value upon an occurrence of an event in the logic input signal and outputting a captured counter value and issuing a trigger signal; and
determining, by a decoder, a decoded value based on the values of the logic input signal and the plurality of consecutive increasingly delayed replicas when the trigger signal is issued and computing a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

13. A method for time capture to measure time between edges of a logic input signal, the method comprising:
receiving the logic input signal;
generating a plurality of consecutive increasingly delayed replicas of the logic input signal, each replica delayed by a fixed delay with respect to a preceding replica;
operating a free running counter clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor;
upon occurrence of an edge in the logic input signal, capturing a counter value of the free running counter and issuing a trigger signal;
determining a decoded value based on the values of the logic input signal and the plurality of consecutive increasingly delayed replicas when the trigger signal is issued; and
computing a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

14. The method according to claim 13 , further comprising setting the clock scale factor to one.

15. The method according to claim 13 , wherein generating the plurality of consecutive increasingly delayed replicas comprises generating a number M of replicas, wherein M=2 N , N being a given integer size factor, and wherein the second scale factor is equal to the integer size factor N minus the first scale factor.

16. The method according to claim 13 , wherein determining the decoded value comprises accessing a first decoding table comprising records that include, as fields, the values of an external signal and of other consecutive increasingly delay

Assignees

• St Microelectronics Srl

Inventors

• D'Angelo Giuseppe

Classifications

• H03K21/02

  Input circuits · CPC title

• H03K5/159

  Applications of delay lines not covered by the preceding subgroups · CPC title

• G04F10/04

  by counting pulses or half-cycles of an AC {(G04F10/005 takes precedence)} · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title