Detector circuit and system for galvanically isolated transmission of digital signals

Patent metadata

Field	Value
Publication number	US-11201766-B2
Application number	US-201916970551-A
Country	US
Kind code	B2
Filing date	Mar 27, 2019
Priority date	Mar 28, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A detector circuit for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs, one input common-mode voltage connection, one alternating voltage coupling, and one differential stage. The detector circuit also includes one operating voltage connection, one operating ground connection, one signal output, one bias current connection, and one rectifier stage. The alternating current coupling includes two capacitors and two resistors. The differential stage includes a first n-channel transistor and a second n-channel transistor. The bias current connection is connected to the differential stage via a third n-channel transistor. The bias current connection is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor. The rectifier stage includes five p-channel transistors.

First claim

What is claimed is:

1. A detector circuit, comprising:
two differential signal inputs;
an input common-mode voltage connection;
an alternating voltage coupling;
a differential stage;
an operating voltage connection;
an operating ground connection;
a signal output;
a bias current connection; and
a rectifier stage;
wherein the alternating voltage coupling includes two capacitors and two resistors, and respective one of the two capacitors being connected to a respective one of the two differential signal inputs, and the two capacitors each being further connected to the differential stage and to the input common-mode voltage connection via the two resistors;
wherein the differential stage including a first n-channel transistor and a second n-channel transistor, and the first n-channel transistor and the second n-channel transistor each being connected to the respective one of the two resistors of the alternating voltage coupling and the respective one of the two capacitors of the alternating voltage coupling;
wherein the bias current connection is connected to the differential stage via a third n-channel transistor, and the bias current connection being connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor;
wherein the operating ground connection is connected to the third n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor;
wherein the rectifier stage includes five p-channel transistors, the first n-channel transistor being connected to a first one of the five p-channel transistors, a fourth one of the five p-channel transistors and a fifth one of the five p-channel transistors, and the second n-channel transistor being connected to a second one of the five p-channel transistors, the fourth one of the p-channel transistors and the fifth one of the five p-channel transistors;
wherein the operating voltage connection is connected to the first one of the five p-channel transistors, the second one of the five p-channel transistors, and a third one of the five p-channel transistors; and
wherein the signal output is connected to the fourth one of the five p-channel transistors and the fifth one of the five p-channel transistors.

2. The detector circuit as recited in claim 1 , wherein the first one of the five p-channel transistors and the second one of the five p-channel transistors are configured in such a way that they supply higher currents than that which are taken up by the first n-channel transistor and the second n-channel transistor when no differential signal is present at the differential signal inputs.

3. The detector circuit as recited in claim 1 , wherein the first n-channel transistor and the second n-channel transistor are configured in such a way that they take up higher currents than that which are supplied by the first one of the five p-channel transistors and the second one of the five p-channel transistors when a high frequency differential signal having an amplitude above a threshold is present at the differential signal inputs.

4. The detector circuit as recited in claim 1 , wherein a drain current from the third n-channel transistor is conducted all the way through the first n-channel transistor or the second n-channel transistor when a high frequency differential signal having an amplitude above a threshold is present at the differential signal inputs.

5. The detector circuit as recited in claim 4 , wherein the fourth one of the five p-channel transistors and the fifth one of the five p-channel transistors are alternately turned on, and unused drain current in each case is conducted from the first one of the five p-channel transistors and the second one of the five p-channel transistors to the signal output when a high frequency differential signal having an amplitude above a threshold is present at the differential signal inputs.

6. A system, comprising:
a transmitter side which includes a transmitter encompassing an on-off keying modulator;
a galvanic isolator joined to the transmitter; and
a receiver side joined to the galvanic isolator and which includes a current comparator, a common-mode control circuit, and a detector circuit connected to the current comparator and the common-mode control circuit, the detector circuit including:
two differential signal inputs;
an input common-mode voltage connection;
an alternating voltage coupling;
a differential stage;
an operating voltage connection;
an operating ground connection;
a signal output;
a bias current connection; and
a rectifier stage;

wherein the alternating voltage coupling includes two capacitors and two resistors, and respective one of the two capacitors being connected to a respective one of the two differential signal inputs, and the two capacitors each being further connected to the differential stage and to the input common-mode voltage connection via the two resistors;
wherein the differential stage including a first n-channel transistor and a second n-channel transistor, and the first n-channel transistor and the second n-channel transistor each being connected to the respective one of the two resistors of the alternating voltage coupling and the respective one of the two capacitors of the alternating voltage coupling;
wherein the bias current connection is connected to the differential stage via a third n-channel transistor, and the bias current connection being connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor;
wherein the operating ground connection is connected to the third n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor;
wherein the rectifier stage includes five p-channel transistors, the first n-channel transistor being connected to a first one of the five p-channel transistors, a fourth one of the five p-channel transistors and a fifth one of the five p-channel transistors, and the second n-channel transistor being connected to a second one of the five p-channel transistors, the fourth one of the p-channel transistors and the fifth one of the five p-channel transistors;
wherein the operating voltage connection is connected to the first one of the five p-channel transistors, the second one of the five p-channel transistors, and a third one of the five p-channel transistors; and
wherein the signal output is connected to the fourth one of the five p-channel transistors and the fifth one of the five p-channel transistors.

Assignees

• Bosch Gmbh Robert

Inventors

• Schubert Andreas

Classifications

• H03F3/45183 Primary

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F2203/45398

  the AAC comprising a voltage generating circuit as bias circuit for the AAC · CPC title

• H03F3/45484

  in differential amplifiers with bipolar transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03F2203/45508

  the CSC comprising a voltage generating circuit as bias circuit for the CSC · CPC title

• H03F2203/45588

  the IC comprising offset compensating means · CPC title