Duty cycle control circuitry for input/output (I/O) margin control

Patent metadata

Field	Value
Publication number	US-11201611-B2
Application number	US-201816218053-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Dec 12, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.

First claim

What is claimed is:

1. An apparatus, comprising:
an input/output (I/O) predriver stage;
an I/O output stage to output a signal for communication with a remote device, the I/O output stage coupled to the predriver stage through a connection between the predriver stage and the output stage, the output stage to be driven by the predriver stage with an alternating current (AC) signal to generate a digital output; and
a control circuit to control a direct current (DC) bias of the connection between the predriver stage and the output stage to provide trim adjustment of a duty cycle of the digital output of the output stage, wherein a change of the DC bias is to shift an intersection point of the AC signal with a transition voltage threshold at which the digital output is to transition from one logic value to another, to change the duty cycle of the digital output of the output stage.

2. The apparatus of claim 1 , wherein the I/O predriver stage comprises an input buffer predriver stage and wherein the I/O output stage comprises an input buffer output stage to output a signal received from the remote device.

3. The apparatus of claim 1 , wherein the I/O predriver stage comprises a driver predriver stage and wherein the I/O output stage comprises a driver output stage to output a signal to transmit to the remote device.

4. The apparatus of claim 1 , wherein the control circuit is to provide a positive DC offset of an output of the predriver stage to cause the AC signal to cross the intersection point at a lower AC signal voltage to cause the output stage to transition in response to lower relative predriver stage output values.

5. The apparatus of claim 1 , wherein the control circuit is to provide a negative DC offset of an output of the predriver stage to cause the AC signal to cross the intersection point at a higher AC signal voltage to cause the output stage to transition in response to higher relative predriver stage output values.

6. The apparatus of claim 1 , wherein the control circuit comprises a current source.

7. The apparatus of claim 1 , wherein the control circuit comprises separate positive DC bias and negative DC bias components.

8. The apparatus of claim 1 , wherein the control circuit comprises a feedforward loop with circuitry of the predriver stage to control the DC bias of the connection negatively responsive to predriver nonlinearity.

9. The apparatus of claim 8 , wherein the control circuit comprises a current source as a current mirror of a current source of the predriver stage.

10. The apparatus of claim 1 , further comprising:
a duty cycle control inline with a current path of an output of the predriver stage.

11. The apparatus of claim 1 , wherein the control circuit is to control the DC bias for a primary signal of a differential signal, and further comprising:
a blending circuit to average duty cycles of the primary and complementary signals to align complementary edges of the primary and complementary signals.

12. The apparatus of claim 1 , wherein the I/O output stage is to output a clock signal.

13. The apparatus of claim 1 , wherein the I/O output stage is to output a data signal.

14. A system, comprising:
a memory device coupled to drive an input/output (I/O) signal line; and
a memory controller coupled to receive a signal from the memory device on the I/O signal line, the memory controller including an input buffer including:
a predriver stage;
an output stage coupled to the predriver stage through a connection between the predriver stage and the output stage, the output stage to be driven by the predriver stage; and
a control circuit to control a direct current (DC) bias of the connection between the predriver stage and the output stage to provide trim adjustment of a duty cycle of a digital output of the output stage, wherein a change of the DC bias is to change the duty cycle of the digital output of the output stage.

15. The system of claim 14 , wherein the output stage has a voltage threshold to trigger transition between high and low output values of the output stage, where the control circuit is to
increase a DC offset of an output of the predriver stage to cause the output stage to transition in response to lower relative predriver stage output values, or,
decrease the DC offset of the output of the predriver stage to cause the output stage to transition in response to higher relative predriver stage output values.

16. The system of claim 14 , wherein the control circuit comprises separate positive DC bias and negative DC bias components.

17. The system of claim 14 , wherein the control circuit comprises a feedforward loop with circuitry of the predriver stage to control the DC bias of the connection negatively responsive to predriver nonlinearity.

18. The system of claim 14 , further comprising:
a duty cycle control inline with a current path of an output of the predriver stage.

19. The system of claim 14 , wherein the control circuit is to control the DC bias for a primary signal of a differential signal, and further comprising:
a blending circuit to average duty cycles of the primary and complementary signals to align complementary edges of the primary and complementary signals.

20. The system of claim 14 , further comprising one or more of:
a host processor device coupled to the memory controller;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.

Assignees

• Intel Corp

Inventors

• Wang Guan
• Tang Qiang
• Maccarrone Agatino Massimo

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title