Oscillator and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11201588-B2
Application number	US-202017124868-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Dec 18, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

An oscillator includes a resonator, a clock signal generation circuit, a clock signal output terminal, an external signal input terminal, an interface circuit, and an interface terminal. The clock signal generation circuit oscillates the resonator to generate a clock signal. The clock signal output terminal outputs the clock signal. An external signal is input to the external signal input terminal. The interface circuit outputs time difference information obtained by measuring a time difference between a transition timing of a first signal based on the external signal input from the external signal input terminal and a transition timing of a second signal based on the clock signal, or frequency information obtained by measuring a frequency of a first clock signal, which is one of the clock signal and the external clock signal, based on a frequency of a second clock signal, which is the other of the clock signal and the external clock signal. The interface terminal is coupled to the interface circuit.

First claim

What is claimed is:

1. An oscillator comprising:
a resonator;
a clock signal generation circuit that oscillates the resonator to generate a clock signal;
a clock signal output terminal that outputs the clock signal;
an external signal input terminal that receives an external signal;
an interface circuit that outputs
time difference information obtained by measuring a time difference between a transition timing of a first signal based on the external signal input from the external signal input terminal and a transition timing of a second signal based on the clock signal, or
frequency information obtained by measuring a frequency of a first clock signal, which is one of the clock signal and the external clock signal, based on a frequency of a second clock signal, which is the other of the clock signal and the external clock signal; and

an interface terminal that is coupled to the interface circuit.

2. The oscillator according to claim 1 , further comprising:
a time-to-digital conversion circuit that obtains the time difference information.

3. The oscillator according to claim 1 , further comprising:
a frequency measurement circuit that obtains the frequency information.

4. The oscillator according to claim 3 , wherein
the frequency measurement circuit includes,
a time-to-digital conversion circuit that measures a time difference between a transition timing of a first signal based on the first clock signal and a transition timing of a second signal based on the second clock signal and outputs time difference information corresponding to the time difference,
a counter circuit that performs count processing based on the first clock signal and the second clock signal and outputs count data, and
an arithmetic circuit that obtains the frequency information by performing an arithmetic operation based on the time difference information and the count data.

5. The oscillator according to claim 1 , wherein
the clock signal generation circuit adjusts a frequency of the clock signal based on frequency adjustment data input via the interface terminal and the interface circuit.

6. The oscillator according to claim 5 , wherein
the clock signal generation circuit includes an oscillation circuit that generates an oscillation clock signal by oscillating the resonator, and
the oscillation circuit adjusts a frequency of the oscillation clock signal based on the frequency adjustment data, and outputs the oscillation clock signal as the clock signal.

7. The oscillator according to claim 5 , wherein
the clock signal generation circuit includes,
an oscillation circuit that generates an oscillation clock signal by oscillating the resonator, and
a fractional-N PLL circuit that receives the oscillation clock signal as a reference clock signal and generates the clock signal, and

the fractional-N PLL circuit adjusts a frequency division ratio of a feedback loop based on the frequency adjustment data.

8. The oscillator according to claim 2 , wherein
the clock signal generation circuit, the time-to-digital conversion circuit, and the interface circuit are provided in one semiconductor substrate.

9. The oscillator according to claim 3 , wherein
the clock signal generation circuit, the frequency measurement circuit, and the interface circuit are provided in one semiconductor substrate.

10. The oscillator according to claim 8 , wherein
the resonator and the semiconductor substrate are housed in a package.

11. The oscillator according to claim 1 , further comprising:
a temperature sensor; and
a temperature compensation circuit that outputs a temperature compensation signal based on a signal from the temperature sensor, wherein
the clock signal generation circuit adjusts a frequency of the clock signal based on the temperature compensation signal.

12. The oscillator according to claim 11 , wherein
the clock signal generation circuit includes an oscillation circuit that generates an oscillation clock signal by oscillating the resonator, and
the oscillation circuit adjusts a frequency of the oscillation clock signal based on the temperature compensation signal and outputs the oscillation clock signal as the clock signal.

13. The oscillator according to claim 11 , wherein
the clock signal generation circuit includes,
an oscillation circuit that generates an oscillation clock signal by oscillating the resonator, and
a fractional-N PLL circuit that receives the oscillation clock signal as a reference clock signal and generates the clock signal, and

the fractional-N PLL circuit adjusts a frequency division ratio of a feedback loop based on the temperature compensation signal.

14. The oscillator according to claim 2 , further comprising:
a first frequency division circuit;
a second frequency division circuit; and
an interface circuit that receives frequency division ratio setting information for setting a first frequency division ratio that is a frequency division ratio of the first frequency division circuit and a second frequency division ratio that is a frequency division ratio of the second frequency division circuit, wherein
the first frequency division circuit frequency-divides an external clock signal input as the external signal by the first frequency division ratio based on the frequency division ratio setting information and outputs a first frequency divided clock signal obtained by frequency division,
the second frequency division circuit frequency-divides the clock signal by the second frequency division ratio based on the frequency division ratio setting information and outputs a second frequency divided clock signal obtained by frequency division, and
the time-to-digital conversion circuit measures a phase difference between the first frequency divided clock signal which is the first signal and the second frequency divided clock signal which is the second signal as the time difference.

15. The oscillator according to claim 3 , further comprising:
a first frequency division circuit;
a second frequency division circuit; and
an interface circuit that receives frequency division ratio setting information for setting a first frequency division ratio that is the frequency division ratio of the first frequency division circuit and a second frequency division ratio that is the frequency division ratio of the second frequency division circuit, wherein
the first frequency division circuit frequency-divides the first clock signal by the first frequency division ratio based on the frequency division ratio setting information and outputs a first frequency divided clock signal obtained by frequency division,
the second frequency division circuit frequency-divides the second clock signal by the second frequency division ratio based on the frequency division ratio setting information and outputs a second frequency divided clock signal obtained by frequency division, and
the frequency measurement circuit obtains the frequency information by measuring a frequency of the first frequency divided clock signal based on a frequency of the second frequency divided clock signal.

16. The oscillator according to claim 2 , wherein
the time-to-digital conversion circuit operates based on the clock signal.

17. The oscillator according to claim 1 , further comprising:
a processing circuit that generates frequency adjustment data according to the time difference information or the frequency information, wherein
the clock signal generation circuit adjusts a frequency of the clock signal based on the frequency adjustment data.

18. The

Assignees

• Seiko Epson Corp

Inventors

• Haneda Hideo
• Sudo Yasuhiro
• Tsutsumi Akio

Classifications

• H03B5/04

  Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G04G3/00

  Producing timing pulses (driving circuits for stepping motors G04C3/14; producing preselected time intervals for use as timing standards G04F5/00; pulse technique in general H03K; control, synchronisation, or stabilisation of generators in general H03L) · CPC title