Semiconductor device including saturation current suppression layer

Patent metadata

Field	Value
Publication number	US-11201239-B2
Application number	US-202016819771-A
Country	US
Kind code	B2
Filing date	Mar 16, 2020
Priority date	Sep 18, 2017
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

First claim

What is claimed is:

1. A semiconductor device comprising
a semiconductor element of inversion-type, including:
a substrate made of semiconductor and having a first conductivity type or a second conductivity type;
a drift layer formed above the substrate, made of semiconductor, having the first conductivity type, and having an impurity concentration smaller than that of the substrate;
a saturation current suppression layer formed above the drift layer and including a plurality of electric field block layers and a plurality of JFET portions, wherein:
the plurality of electric field block layers are made of semiconductor, have the second conductivity type, and are arranged in a stripe manner;
a longer direction of a respective electric field block layer is one direction;
the plurality of JFET portions are made of semiconductor, have the first conductivity type, and are arranged in a stripe manner;
a longer direction of a respective JFET portion is the one direction; and
the plurality of electric field block layers and the plurality of JFET portions are alternately arranged,

a base region formed above the saturation current suppression layer, made of semiconductor, and having the second conductivity type;
a source region formed above the base region, made of semiconductor, having the first conductivity type, and having a first conductivity type impurity concentration larger than that of the drift layer;
a plurality of trench gate structures arranged in a stripe manner, wherein:
a longer direction of a respective trench gate structure intersects with the one direction;
a respective gate structures includes a gate insulating film and a gate electrode;
the gate insulating film covers an inner wall surface of a gate trench;
the gate trench is formed from a surface of the source region and is deeper than the base region; and
the gate electrode is arranged on the gate insulating film,

an interlayer insulating film covering the gate electrode and the gate insulating film, wherein a contact hole is formed in the interlayer insulating film;
a source electrode electrically connected to the source region via the contact hole; and
a drain electrode formed on a back side of the substrate,
wherein:
a respective JFET portion includes, in a trench penetrating the electric field block layer and having a bottom surface to expose the drift layer,
a first layer formed on the bottom surface and a side surface of the trench, and having a first conductivity type impurity concentration larger than that of the drift layer and
a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than that of the first layer; and

by applying a gate voltage to the gate electrode and applying a voltage for a normal operation to the drain electrode as a drain voltage, a channel region is formed in a portion of the base region that contacts with the trench gate structure and a current flows between the source electrode and the drain electrode via the source region and the JEFT portion.

2. The semiconductor device according to claim 1 , wherein
a JFET pitch which is an interval of the plurality of JEFT portions is smaller than a cell pitch which is an interval of the trench gates.

3. The semiconductor device according to claim 1 , wherein
the first layer constitutes a depletion layer adjustment layer that:
suppresses an extension amount of a depletion layer extending from a respective electric field block layer toward a respective second layer to enable the current to flow via a respective JFET portion, when the voltage for the normal operation is applied as the drain voltage; and
causes the respective JFET portion to be pinched off by the depletion layer, when a voltage larger than the voltage for normal operation is applied as the drain voltage.

4. The semiconductor device according to claim 1 , wherein:
a dimension of a respective JEFT portion in an arrangement direction of the plurality of JFET portions is 0.2 μm to 0.5 μm.

5. The semiconductor device according to claim 1 , wherein:
a respective electric field block layer has a drift layer near potion and a drift layer far portion, and the second conductivity type impurity concentration of the drift layer near potion is smaller than that of the drift layer far portion.

6. The semiconductor device according to claim 1 , wherein:
a respective electric field block layer has a lower layer portion and an upper layer portion;
the lower layer portion contacts with the drift layer;
the upper layer portion is formed above the lower layer portion; and
the second conductivity type impurity concentration of the upper layer portion is larger than that of the lower layer portion.

7. The semiconductor device according to claim 6 , wherein:
the second conductivity type impurity concentration of the lower layer portion gradually increases in a direction from the drift layer to the upper layer portion.

8. The semiconductor device according to claim 1 , wherein:
a dimension of a respective electric field block layer in an arrangement direction of the plurality of electric field block layers is 0.3 μm to 0.8 μm.

Assignees

• Denso Corp

Inventors

• Takeuchi Yuichi
• Ebihara Yasuhiro
• Sugimoto Masahiro
• Yamashita Yusuke

Classifications

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title