Semiconductor device

Patent metadata

Field	Value
Publication number	US-11201236-B2
Application number	US-202016778092-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Feb 4, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A semiconductor device includes a semiconductor body having opposing first and second surfaces in a vertical direction, a first semiconductor region of a first doping type electrically coupled to a first terminal, a second semiconductor region of a second doping type electrically coupled to a second terminal, and a third semiconductor region of the second doping type, but less highly doped than the second semiconductor region, extending in an active region of the semiconductor device from the first to the second semiconductor region in the vertical direction. A horizontal field-stop-region of the first doping type extends in an edge region of the device from the first semiconductor region into the semiconductor body in the vertical direction, such that it directly adjoins the first and second semiconductor regions. A horizontal compensation region of the first doping type extends from the horizontal field-stop-region into the second semiconductor region in a horizontal direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor body comprising a first surface and a second surface opposite to the first surface in a vertical direction;
a first semiconductor region of a first doping type and electrically coupled to a first terminal;
a second semiconductor region of a second doping type and electrically coupled to a second terminal;
a third semiconductor region of the second doping type, but less highly doped than the second semiconductor region, extending in an active region of the semiconductor device from the first semiconductor region to the second semiconductor region in the vertical direction;
a horizontal field-stop-region of the first doping type and extending in an edge region of the semiconductor device from the first semiconductor region into the semiconductor body in the vertical direction, such that the horizontal field-stop-region directly adjoins the first semiconductor region and the second semiconductor region; and
a horizontal compensation region of the first doping type and extending from the horizontal field-stop-region into the second semiconductor region in a horizontal direction which is perpendicular to the vertical direction.

2. The semiconductor device of claim 1 , wherein the horizontal field-stop-region surrounds the second semiconductor region and the third semiconductor region in a horizontal plane.

3. The semiconductor device of claim 1 , wherein the second semiconductor region has a first width in the horizontal direction, wherein the horizontal compensation region has a second width in the horizontal direction, and wherein the second width is smaller than the first width.

4. The semiconductor device of claim 1 , wherein the second semiconductor region has a first thickness in the vertical direction, wherein the horizontal compensation region has a second thickness in the vertical direction, and wherein the second thickness is smaller than the first thickness.

5. The semiconductor device of claim 1 , wherein a dopant dose of the horizontal compensation region is chosen from a range of ±30% of a dopant dose of the second semiconductor region.

6. The semiconductor device of claim 1 , wherein the horizontal field-stop-region comprises a first section and a second section, and wherein the second section is arranged adjacent to the horizontal compensation region.

7. The semiconductor device of claim 1 , wherein the second semiconductor region is a vertical field-stop-region, and wherein the semiconductor device further comprises a drain region arranged adjacent to the second semiconductor region in the vertical direction.

8. The semiconductor device of claim 7 , further comprising a plurality of transistor cells at least partly integrated in the active region, each transistor cell comprising a source region, a body region formed by a section of the first semiconductor region, a drift region formed by a section of the third semiconductor region and separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region.

9. The semiconductor device of claim 8 , further comprising vertical compensation regions extending from the body regions towards the second semiconductor region.

10. The semiconductor device of claim 8 , further comprising a source electrode arranged above the first surface and electrically connected to the source regions of the plurality of transistor cells.

11. The semiconductor device of claim 8 , further comprising:
a drain electrode electrically connected to the drain region; and
a gate pad electrically connected to the gate electrodes of the plurality of transistor cells,
wherein the drain electrode and the gate pad are arranged above the second surface.

12. The semiconductor device of claim 1 , further comprising an intrinsic semiconductor region arranged between the first semiconductor region and the second semiconductor region in the vertical direction, and arranged between the third semiconductor region and the horizontal field-stop-region in the horizontal direction.

13. A method, comprising:
forming a second semiconductor region in a first layer of semiconductor material, by implanting ions of a second doping type;
forming a second section of a horizontal field-stop-region in the first layer of semiconductor material, by implanting ions of a first doping type, wherein the second section of the horizontal field-stop-region adjoins the second semiconductor region in a horizontal direction;
forming a horizontal compensation region in the second semiconductor region, by implanting ions of the first doping type, wherein the horizontal compensation region extends from the second section of the horizontal field-stop-region into the second semiconductor region in the horizontal direction;
depositing a second layer of semiconductor material on the first layer of semiconductor material;
forming a third semiconductor region of the second doping type in the second layer of semiconductor material;
forming a first semiconductor region of the first doping type in the second layer of semiconductor material, wherein the third semiconductor region is arranged between the first semiconductor region and the second semiconductor region in a vertical direction that is perpendicular to the horizontal direction; and
forming a first section of the horizontal field-stop-region of the first doping type, wherein the first section extends from the first semiconductor region to the second section in the vertical direction.

14. The method of claim 13 , wherein the first layer of semiconductor material is either a junction termination extension region of at least one of the first doping type and the second doping type, or is an intrinsic or undoped layer.

15. The method of claim 13 , further comprising:
forming a plurality of transistor cells, each transistor cell comprising a source region, a body region formed by a section of the first semiconductor region, a drift region formed by a section of the third semiconductor region and separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region.

16. The method of claim 15 , further comprising:
forming vertical compensation regions extending from the body regions towards the second semiconductor region.

17. The method of claim 15 , further comprising:
forming a source electrode electrically connected to the source regions of the plurality of transistor cells.

18. The method of claim 15 , further comprising:
forming a drain electrode electrically connected to the drain region; and
forming a gate pad electrically connected to the gate electrodes of the plurality of transistor cells.

19. The method of claim 13 , further comprising:
forming an intrinsic semiconductor region arranged between the first semiconductor region and the second semiconductor region in the vertical direction, and arranged between the third semiconductor region and the horizontal field-stop-region in the horizontal direction.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Fischer Bjoern

Classifications

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title