Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11201178-B2
Application number	US-201716072325-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Apr 25, 2017
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

An array substrate, a manufacturing method thereof, and a display device are disclosed. The array substrate includes: a base substrate; a gate line located on the base substrate and extending in a first direction; a data line located on the base substrate and extending in a second direction; the gate line and the data line crossing each other to define an orthographic projection of a pixel region on the base substrate; an organic film located on the gate line and the data line and located in the pixel region; and a pixel electrode located on the organic film in the pixel region. The organic film located directly above the data line has a first thickness, the organic film located directly below the pixel electrode has a second thickness, and the first thickness is greater than the second thickness.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a gate line, located on the base substrate and extending in a first direction;
a data line, located on the base substrate and extending in a second direction;
the gate line and the data line crossing each other to define an orthographic projection of a pixel region on the base substrate;
an organic film, located on the gate line and the data line, and located in the pixel region; and
a pixel electrode, located on the organic film in the pixel region,
wherein the organic film located directly above the data line has a first thickness, the organic film located directly below the pixel electrode has a second thickness, the first thickness is greater than the second thickness, and the organic film located directly above the data line and the organic film located directly below the pixel electrode are integrated films.

2. The array substrate according to claim 1 , further comprising:
a thin film transistor, located in the pixel region, wherein the thin film transistor is located between the organic film and the base substrate, and the pixel electrode is connected to a drain electrode of the thin film transistor through a via hole in the organic film, a thickness of the organic film located directly above the thin film transistor is equal to the first thickness.

3. The array substrate according to claim 2 , wherein a thickness of the organic film located directly above the gate line is equal to the first thickness.

4. The array substrate according to claim 2 , wherein a ratio of the second thickness to the first thickness is not less than 0.5.

5. The array substrate according to claim 1 , wherein a thickness of the organic film located directly above the gate line is equal to the first thickness.

6. The array substrate according to claim 5 , wherein a ratio of the second thickness to the first thickness is not less than 0.5.

7. The array substrate according to claim 1 , wherein a ratio of the second thickness to the first thickness is not less than 0.5.

8. The array substrate according to claim 1 , wherein the pixel region further comprises a common electrode, the common electrode is located on a side of the organic film away from the base substrate, and is overlapped with at least one of the data line and the gate line in a direction perpendicular to the base substrate.

9. The array substrate according to claim 8 , wherein the common electrode is located on a side of the pixel electrode away from the base substrate or between the pixel electrode and the organic film.

10. The array substrate according to claim 8 , wherein the common electrode is a transparent conductive electrode.

11. A display device, comprising the array substrate according to claim 1 .

12. The array substrate according to claim 1 , further comprising:
a passivation layer, located on a side of the organic film away from the base substrate, at least part of the passivation layer being in contact with the organic film,
wherein a distance between the base substrate and a part of the passivation layer located directly above the data line is greater than a distance between the base substrate and a part of the passivation layer located directly below the pixel electrode.

13. A manufacturing method of an array substrate, comprising:
forming a gate line extending in a first direction and a data line extending in a second direction on a base substrate, wherein the gate line and the data line cross each other to define an orthographic projection of a pixel region on the base substrate;
forming an organic film on the gate line and the data line, and in the pixel region; and
forming a pixel electrode on the organic film, the pixel electrode being located in the pixel region,
wherein the organic film located directly above the data line has a first thickness, the organic film located directly below the pixel electrode has a second thickness, the first thickness is greater than the second thickness, and
the organic film located directly above the data line and the organic film located directly below the pixel electrode are formed by a one-step patterning process.

14. The manufacturing method of the array substrate according to claim 13 , further comprising:
forming a thin film transistor in the pixel region, wherein the thin film transistor is formed between the organic film and the base substrate, the pixel electrode is connected to a drain electrode of the thin film transistor through a via hole in the organic film, a thickness of the organic film located directly above the thin film transistor is equal to the first thickness.

15. The manufacturing method of the array substrate according to claim 13 , wherein the organic film is formed by using a half tone mask process.

16. The manufacturing method of the array substrate according to claim 13 , further comprising:
forming a common electrode in the pixel region, wherein the common electrode is formed on a side of the organic film away from the base substrate, and is overlapped with at least one of the data line and the gate line in a direction perpendicular to the base substrate.

17. The manufacturing method of the array substrate according to claim 16 , wherein the common electrode is formed on a side of the pixel electrode away from the base substrate or between the pixel electrode and the organic film.

18. An array substrate, comprising:
a base substrate;
a gate line, located on the base substrate and extending in a first direction;
a data line, located on the base substrate and extending in a second direction;
the gate line and the data line crossing each other to define an orthographic projection of a pixel region on the base substrate;
an organic film, located on the gate line and the data line, and located in the pixel region; and
a pixel electrode, located on the organic film in the pixel region,
wherein the organic film located directly above the data line has a first thickness, the organic film located directly below the pixel electrode has a second thickness, the first thickness is greater than the second thickness, and a ratio of the second thickness to the first thickness is not less than 0.5.

19. The array substrate according to claim 18 , further comprising:
a thin film transistor, located in the pixel region, wherein the thin film transistor is located between the organic film and the base substrate, and the pixel electrode is connected to a drain electrode of the thin film transistor through a via hole in the organic film, a thickness of the organic film located directly above the thin film transistor is equal to the first thickness.

20. The array substrate according to claim 18 , wherein a thickness of the organic film located directly above the gate line is equal to the first thickness.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Chen Chuanbao
• Yin Xiaobin
• Ma Juncai

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title