Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11201155-B2
Application number	US-201916679335-A
Country	US
Kind code	B2
Filing date	Nov 11, 2019
Priority date	Dec 14, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

The instant disclosure discloses a semiconductor device comprising a substrate having a cell region; a device layer over the substrate; a plurality of capacitor lower electrodes over the device layer in the cell region, each of the capacitor lower electrodes has a U-shaped profile defining an inner surface in a cross section; a capacitor dielectric liner on the inner surfaces of the capacitor lower electrodes; and a SiGe layer over the capacitor dielectric liner, wherein the SiGe layer has a Ge concentration distribution that has a greatest value at a middle portion of the SiGe layer and decreases there-from upwardly and downwardly along a thickness direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a cell region;
a device layer over the substrate;
a plurality of capacitor lower electrodes over the device layer in the cell region, each of the capacitor lower electrodes has a U-shaped profile defining an inner surface in a cross section;
a capacitor dielectric liner on the inner surfaces of the capacitor lower electrodes; and
a SiGe layer over the capacitor dielectric liner, wherein the SiGe layer has a Ge concentration distribution that has a greatest value at a middle portion of the SiGe layer and decreases there-from upwardly and downwardly along a thickness direction.

2. The semiconductor device of claim 1 , further comprising
a metallic material disposed between the capacitor dielectric liner and the SiGe layer,
wherein the metallic material filling in and between the U-shaped profile of the capacitor lower electrodes; and
wherein the SiGe layer has a substantially planar profile extending across the plurality of the capacitor lower electrodes.

3. The semiconductor device of claim 1 , further comprising
a contact feature penetrating an interlayer dielectric layer and electrically connects the SiGe layer and an upper metal line over the dielectric layer.

4. The semiconductor device of claim 1 , further comprising
a top conductive layer disposed over the SiGe layer;
an interlayer dielectric layer formed over the top conductive layer; and
a contact feature penetrating the interlayer dielectric layer that enables vertical electrical connection between the top conductive layer and an upper metal line over the interlayer dielectric layer.

5. The semiconductor device of claim 1 ,
wherein a Ge content of the SiGe layer in the middle potion is in a range from about 75 to 95 atomic %.

6. The semiconductor device of claim 1 ,
wherein the Ge concentration distribution of the SiGe layer decreases nonlinearly from the middle portion upwardly and downwardly along a thickness direction.

7. The semiconductor device of claim 1 ,
wherein the Ge concentration distribution of the SiGe layer decreases linearly from the middle portion upwardly and downwardly along the thickness direction.

8. The semiconductor device of claim 1 ,
wherein the Ge concentration distribution of the SiGe layer has a step-shaped profile along the thickness direction.

9. The semiconductor device of claim 1 , further comprising
a plurality of the SiGe layers stacked over the capacitor dielectric liner.

10. The semiconductor device of claim 9 ,
wherein the stacked SiGe layers has a thickness in a range from about 1200 to about 1600 Å; and
wherein a thickness of the middle portion of each of the SiGe layers has a range from about 100 to about 200 Å.

11. The semiconductor device of claim 1 , further comprises
a top conductive layer formed on the SiGe layer; and
a buffer layer formed on the top conductive layer, wherein the lattice constant of the buffer layer is greater than that of the top conductive layer.

12. The semiconductor device of claim 11 ,
wherein a major metal content in the buffer layer is different from that in the top conductive layer.

13. A method, comprising
receiving a substrate;
disposing a lower electrode over the substrate, wherein the lower electrode has a U-shaped profile in a cross section thereof;
disposing a dielectric liner on an inner surface of the lower electrode;
disposing a metallic material filling the U-shaped profile of the lower electrode; and
performing a SiGe layer formation process to dispose a SiGe layer across top surface of the metallic material, wherein the SiGe layer has a Ge concentration distribution that has a greatest value at a middle portion thereof and decreases there-from upwardly and downwardly along a thickness direction.

14. The method of claim 13 ,
wherein the performing the SiGe layer formation process comprises
supplying, in a cycle period, silane-based gas and germanium-based gas over the semiconductor device, wherein a flow rate ratio between silane-based gas and germanium-based gas is raised and then reduced during the cycle period.

15. The method of claim 14 ,
wherein the cycle period includes an initial session, an intermediate session and a final session;
wherein, in the initial session, the flow rate ratio is set in a range from about 10% to 30%;
wherein, in the intermediate session, the flow rate ratio is set in a range 5 from about 30% to 90%; and
wherein in the final session, the flow rate ratio is set in a range from about 10% to 30%.

16. The method of claim 14 , wherein a duration length ratio between the intermediate session and the initial session has a range of about 2 to about 3.

17. The method of claim 15 , wherein a duration length ratio between the intermediate session and the final session has a range of about 2 to about 3.

18. The method of claim 13 , further comprising
performing a plurality of the SiGe layer formation process to form a plurality of the SiGe layers stacked over the interlayer dielectric layer.

19. The method of claim 18 , further comprising
wherein a thickness of the stacked SiGe layers is in a range from about 1200 to about 1600 Å.

Assignees

• Xia Tai Xin Semiconductor Qing Dao Ltd

Inventors

• Lee Sang-Woo
• Choi Keewoung
• Kim Sung-Ki

Classifications

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H01L27/10823

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L28/75

  Electricity · mapped topic