Devices and methods to store an initialization state

Patent metadata

Field	Value
Publication number	US-11200940-B2
Application number	US-201916683192-A
Country	US
Kind code	B2
Filing date	Nov 13, 2019
Priority date	Nov 13, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

First claim

What is claimed is:

1. A memory array comprising:
a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, wherein each of the memory cells is configured to store memory data; and
one or more initialization columns corresponding to at least one of the plurality of memory columns,
wherein an initialization state of a memory row of the memory cells is configured to:
prevent unauthorized read access; and
be stored in:
the memory row;
or
a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

2. The memory array of claim 1 , wherein each of the plurality of memory cells is coupled to a first and second bit-line, and wherein the first and second bit-lines are controlled by read/write circuitry coupled to the memory array.

3. The memory array of claim 1 , wherein each of the one or more initialization columns comprises four memory cells in each physical row.

4. The memory array of claim 1 , wherein each row of the plurality of memory rows is coupled to a word-line.

5. The memory array of claim 1 , wherein the memory array comprises one initialization column for the plurality of memory columns.

6. The memory array of claim 1 , wherein the memory array comprises one initialization column for one of: each memory column of the plurality of memory columns, every two memory columns of the plurality of memory columns, every four memory columns of the plurality of memory columns, every eight memory columns of the plurality of memory columns or every sixteen memory columns of the plurality of memory columns.

7. The memory array of claim 1 , wherein each bit-cell of the initialization column is configured to store an initialization state of a corresponding row of the memory array.

8. The memory array of claim 1 , wherein respective write driver circuits are coupled to the one or more memory rows, and wherein the respective write driver circuits are configured to write data to the one or more memory rows.

9. The memory array of claim 8 , wherein the respective write driver circuits are configured to transmit memory data based on an incoming data signal, a write enable setting, a clock signal, and a column address.

10. The memory array of claim 9 , wherein respective one or more initialization column write driver circuits are coupled to the one or more initialization columns, and wherein the one or more initialization column write driver circuits are configured to set an initialization bit for the one or more initialization columns based on the one or more written memory rows.

11. The memory array of claim 10 , wherein the respective one or more initialization column write driver circuits are configured to transmit the initialization bit based on an incoming data signal, a write enable setting, a clock signal, and an initialization column address.

12. The memory array of claim 1 , wherein respective read driver circuits are coupled to each of the one or more memory columns and one or more initialization columns, wherein each of the one or more memory columns and one or more initialization columns are configured for concurrent read operations.

13. The memory array of claim 12 , wherein the read driver circuits are configured to clamp one or more read data outputs to a “0” data value when an initialization bit is unset, and wherein the read/write driver circuitry are configured to permit data signals for read data outputs when an initialization bit is set.

14. The memory array of claim 1 , wherein each of the memory cells comprises a resettable memory cell configured to reset initialization bits in a memory cycle, wherein each of the resettable memory cells comprises a NAND gate coupled to a respective reset wire, wherein the respective reset wire is coupled to read and write circuitry, and wherein each of the one or more memory columns comprises the respective reset wire.

15. A method comprising:
providing a plurality of memory cells of a memory array apportioned into a plurality of memory columns, a plurality of memory rows, and one or more initialization columns, wherein each of the memory cells is configured to store memory data, wherein each of the memory rows corresponds to one or more memory words; and
storing an initialization state configured to prevent unauthorized read access and corresponding to a memory word of the one or more memory words in: a memory row or a memory cell of the one or more initialization columns.

16. The method of claim 15 , further comprising:
resetting, in a single memory cycle, the initialization state corresponding to the memory word of the one or more memory words.

17. An integrated circuit comprising:
a memory array apportioned into a plurality of memory columns, a plurality of memory rows, and one or more initialization columns, wherein each of the memory cells is configured to store memory data; and
word-line driver circuitry coupled to the memory array and configured to select a word-line coupled to one or more of the memory cells;
wherein an initialization state corresponding to the memory data is configured to:
prevent unauthorized read access; and
be stored in:
a memory row of the plurality of memory rows;
or
a memory cell of the one or more initialization columns.

18. The integrated circuit of claim 17 , further comprising:
read/write circuitry comprising respective read driver circuitry and write driver circuitry for each of the plurality of memory columns and respective read driver circuitry and respective initialization column write driver circuitry for the one or more initialization columns.

19. The integrated circuit of claim 18 , wherein the respective write driver circuitries are configured to transmit memory data based on an incoming data signal, a write enable setting, a clock signal, and a column address, and wherein the respective initialization column write circuitries are configured to transmit the initialization bit based on an incoming data signal, a write enable setting, a clock signal, and an initialization column address.

20. The integrated circuit of claim 18 , wherein the respective read driver circuitries are configured to clamp one or more read data outputs to a “0” data value when an initialization bit is unset, and wherein the read/write driver circuitries are configured to permit data signals for read data outputs when an initialization bit is set.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Prabhat Pranay
• Myers James Edward
• Knight Graham Peter

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/4072 Primary

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title