Method and device for the initial programming of a secondary computer

Patent metadata

Field	Value
Publication number	US-11200195-B2
Application number	US-201816631975-A
Country	US
Kind code	B2
Filing date	Jun 11, 2018
Priority date	Jul 18, 2017
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A method for the initial programming of a secondary computer. The method includes configuring a serial interprocessor interface between the secondary computer and a main computer, and data are written via the interface to a flash memory of the secondary computer.

First claim

What is claimed is:

1. A method for an initial programming, by a main computer of a system, of a secondary computer of the system that is a slave of the main computer, the secondary computer being configured to execute processes that produce results that the secondary computer provides to the main computer or to which the main computer has access via a serial interprocessor interface (SIPI), the initial programming being with specified data, the method comprising the following steps:
during a booting of the secondary computer in a first boot mode, a boot loader of the system determining whether a flash memory of the secondary computer includes a valid program start address; and
responsive to a result of the determination being that the valid program start address is not recognized in the flash memory of the secondary computer:
changing the booting to a second boot mode of the system that uses the SIPI between the secondary computer and the main computer; and
in the second boot mode, the main computer controlling a writing of the data, via the SIPI, to the flash memory of the secondary computer so that the flash memory thereby includes the valid program start address for a subsequent booting of the secondary computer.

2. The method as recited in claim 1 , wherein the changing of the booting to the second boot mode includes configuring a low-voltage differential signal (LVDS) output, an LVDS input, and a system clock of the SIPI.

3. The method as recited in claim 1 , wherein before the writing, the data are communicated to the main computer via a field bus.

4. The method as recited in claim 3 , wherein the communication takes place through a driver module for the field bus, having a transmitter and a receiver.

5. The method as recited in claim 1 , wherein the data are communicated via programming points on a circuit board that is common to the secondary computer and the main computer.

6. The method as recited in claim 1 , wherein the main computer receives the data from a programming station, and the writing is performed by the main computer.

7. The method as recited in claim 1 , wherein, via the SIPI, the main computer loads a program to a direct access memory of the secondary computer and communicates the data to the secondary computer, and wherein the writing is performed by the program.

8. A non-transitory machine-readable storage medium on which is stored a computer program for an initial programming, by a main computer of a system, of a secondary computer of the system that is a slave of the main computer, the secondary computer being configured to execute processes that produce results that the secondary computer provides to the main computer or to which the main computer has access via a serial interprocessor interface (SIPI), the initial programming being with specified data, the computer program, when executed by the system, causing the system to perform the following steps:
during a booting of the secondary computer in a first boot mode, a boot loader of the system determining whether a flash memory of the secondary computer includes a valid program start address; and
responsive to a result of the determination being that the valid program start address is not recognized in the flash memory of the secondary computer:
changing the booting to a second boot mode of the system that uses the SIPI between the secondary computer and the main computer; and
in the second boot mode, the main computer controlling a writing of the data, via the SIPI, to the flash memory of the secondary computer so that the flash memory thereby includes the valid program start address for a subsequent booting of the secondary computer.

9. A system comprising:
a main computer;
a serial interprocessor interface (SIPI); and
a secondary computer;
wherein:
the secondary computer is configured to execute processes that produce results that the secondary computer is configured to provide to the main computer or to which the main computer has access via the SIPI; and
the system is configured to perform a method for an initial programming of the secondary computer with specified data, the method comprising:
during a booting of the secondary computer in a first boot mode, a boot loader of the system determining whether a flash memory of the secondary computer includes a valid program start address; and
responsive to a result of the determination being that the valid program start address is not recognized in the flash memory of the secondary computer:
changing the booting to a second boot mode of the system that uses the SIPI between the secondary computer and the main computer; and
in the second boot mode, the main computer controlling a writing of the data, via the SIPI, to the flash memory of the secondary computer so that the flash memory thereby includes the valid program start address for a subsequent booting of the secondary computer.

Assignees

• Bosch Gmbh Robert

Inventors

• Becker Eugen
• Schreiber Matthias
• Aue Axel

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/124

  where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title