Graphics engine reset and recovery in a multiple graphics context execution environment

Patent metadata

Field	Value
Publication number	US-11200063-B2
Application number	US-201816143777-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.

First claim

We claim:

1. A computing system comprising:
a memory device;
a host processor coupled to the memory device; and
a graphics processor including graphics hardware and logic to:
trigger an idle state in a first command streamer in response to a request to reset a second command streamer that shares the graphics hardware with the first command streamer, wherein the first command streamer and the second command streamer are to be executed via a first set of execution units on a render engine and a second set of execution units on a compute engine, wherein the render engine and the compute engine share a general purpose front end having multiple video front ends to execute work items associated with the first set of execution units and the second set of execution units,
determine an event type associated with the request, and
conduct the reset based on the event type, wherein a reset of a render command streamer associated with the render engine or a compute command streamer associated with the compute engine are to enhance reliability by combining the triggering of idle states in dependent command streamers.

2. The computing system of claim 1 , wherein the logic is to invalidate one or more contexts in the graphics hardware based on the event type.

3. The computing system of claim 2 , wherein a proxy context and a direct context are invalidated if the event type is a host reset request.

4. The computing system of claim 2 , wherein a hung context is invalidated if the event type is an expiry reset request.

5. The computing system of claim 1 , wherein the reset includes a media reset flow if the event media type is a media reset request.

6. The computing system of claim 1 , wherein the logic is to send a reset completion message to a host processor, and wherein the memory device includes instructions, which when executed by the host processor, cause the host processor to acknowledge the reset completion message with a special work item.

7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
trigger an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer, wherein the first command streamer and the second command streamer are to be executed via a first set of execution units on a render engine and a second set of execution units on a compute engine, wherein the render engine and the compute engine share a general purpose front end having multiple video front ends to execute work items associated with the first set of execution units and the second set of execution units;
determine an event type associated with the request; and
conduct the reset based on the event type, wherein a reset of a render command streamer associated with the render engine or a compute command streamer associated with the compute engine are to enhance reliability by combining the triggering of idle states in dependent command streamers.

8. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to invalidate one or more contexts in the graphics hardware based on the event type.

9. The semiconductor apparatus of claim 8 , wherein a proxy context and a direct context are invalidated if the event type is a host reset request.

10. The semiconductor apparatus of claim 8 , wherein a hung context is invalidated if the event type is an expiry reset request.

11. The semiconductor apparatus of claim 7 , wherein the reset includes a media reset flow if the event media type is a media reset request.

12. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to send a reset completion message to a host processor.

13. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing device, cause the computing device to:
trigger an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer, wherein the first command streamer and the second command streamer are to be executed via a first set of execution units on a render engine and a second set of execution units on a compute engine, wherein the render engine and the compute engine share a general purpose front end having multiple video front ends to execute work items associated with the first set of execution units and the second set of execution units;
determine an event type associated with the request; and
conduct the reset based on the event type, wherein a reset of a render command streamer associated with the render engine or a compute command streamer associated with the compute engine are to enhance reliability by combining the triggering of idle states in dependent command streamers.

14. The at least one non-transitory computer readable storage medium of claim 13 , wherein the instructions, when executed, cause the computing device to invalidate one or more contexts in the graphics hardware based on the event type.

15. The at least one non-transitory computer readable storage medium of claim 14 , wherein a proxy context and a direct context are invalidated if the event type is a host reset request.

16. The at least one non-transitory computer readable storage medium of claim 14 , wherein a hung context is invalidated if the event type is an expiry reset request.

17. The at least one non-transitory computer readable storage medium of claim 13 , wherein the reset includes a media reset flow if the event media type is a media reset request.

18. The at least one non-transitory computer readable storage medium of claim 13 , wherein the instructions, when executed, cause the computing device to send a reset completion message to a host processor.

19. A method comprising:
triggering an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer, wherein the first command streamer and the second command streamer are executed via a first set of execution units on a render engine and a second set of execution units on a compute engine share a general purpose front end having multiple video front ends to execute work items associated with the first set of execution units and the second set of execution units;
determining an event type associated with the request; and
conducting the reset based on the event type, wherein a reset of a render command streamer associated with the render engine or a compute command streamer associated with the compute engine are to enhance reliability by combining the triggering of idle states in dependent command streamers.

20. The method of claim 19 , further comprising invalidating one or more contexts in the graphics hardware based on the event type.

21. The method of claim 20 , wherein a proxy context and a direct context are invalidated if the event type is a host reset request.

22. The method of claim 20 , wherein a hung context is invalidated if the event type is an expiry reset request.

23. The method of claim 19 , wherein the reset includes a media reset flow if the event type is a media reset request.

Assignees

• Intel Corp

Inventors

• Chheda Harsh
• Pendluru Nishanth Reddy
• Koston Joseph
• Crawford Eric R

Classifications

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F1/24

  Resetting means · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title