Display panel and display device

Patent metadata

Field	Value
Publication number	US-11199573-B2
Application number	US-202016851590-A
Country	US
Kind code	B2
Filing date	Apr 17, 2020
Priority date	Apr 17, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A display panel includes: a pixel region comprising a plurality of pixels; an open/short test region comprising a plurality of open/short test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal, wherein the plurality of stages is spaced apart by a first distance from the pixel region, and the dummy stage is spaced apart by a second distance greater than the first distance from the open/short test region.

First claim

What is claimed is:

1. A display panel comprising:
a pixel region comprising a plurality of pixels;
an open/short test region comprising a plurality of open/short test pads;
a dummy stage configured to generate a carry signal in response to a scan start signal; and
a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal,
wherein the plurality of stages is spaced apart by a first distance from the pixel region, and the dummy stage is spaced apart by a second distance greater than the first distance from the open/short test region.

2. The display panel of claim 1 , wherein the second distance between the open/short test region and the dummy stage is greater than or equal to a reference distance.

3. The display panel of claim 1 , wherein a width of the dummy stage is narrower than a width of each of the plurality of stages.

4. The display panel of claim 1 , wherein each of the plurality of stages includes:
a first circuit portion configured to operate in response to a previous carry signal; and
a first buffer portion controlled by the first circuit portion to output a corresponding scan signal of the plurality of scan signals,
wherein the dummy stage includes:
a second circuit portion configured to operate in response to the scan start signal; and
a second buffer portion controlled by the second circuit portion, and
wherein a width of the second buffer portion of the dummy stage is narrower than a width of the first buffer portion of each of the plurality of stages.

5. The display panel of claim 4 , wherein a size of at least one transistor included in the second buffer portion is smaller than a size of at least one transistor included in the first buffer portion.

6. The display panel of claim 4 , wherein each of the first circuit portion and the second circuit portion includes:
a control node charging block configured to charge an internal control node in response to the scan start signal or the previous carry signal;
an inverter block configured to control an internal inverted control node based on a voltage of the internal control node;
a control node holding block configured to hold the voltage of the internal control node;
a carry block configured to generate a current carry signal in response to the voltage of the internal control node; and
a control node discharging block configured to discharge the internal control node in response to a next carry signal,
wherein each of the first buffer portion and the second buffer portion includes:
a scan signal outputting block configured to generate the corresponding scan signal in response to the voltage of the internal control node, and
wherein a size of the scan signal outputting block of the second buffer portion is smaller than a size of the scan signal outputting block of the first buffer portion.

7. The display panel of claim 6 , wherein the scan signal outputting block of the first buffer portion is coupled to a corresponding scan line, and outputs the corresponding scan signal to the corresponding scan line, and
wherein the scan signal outputting block of the second buffer portion is not coupled to a scan line.

8. The display panel of claim 6 , wherein each of the first circuit portion and the second circuit portion further includes:
a sensing block configured to control the internal control node based on a sensing on signal and a sensing clock signal,
wherein each of the first buffer portion and the second buffer portion further includes:
a sensing signal outputting block configured to generate a corresponding sensing signal of a plurality of sensing signals in response to the voltage of the internal control node, and wherein a size of the sensing signal outputting block of the second buffer portion is smaller than a size of the sensing signal outputting block of the first buffer portion.

9. The display panel of claim 8 , wherein the sensing signal outputting block of the first buffer portion is coupled to a corresponding sensing control line, and is configured to output the corresponding sensing signal to the corresponding sensing control line, and
wherein the sensing signal outputting block of the second buffer portion is not coupled to a sensing control line.

10. The display panel of claim 1 , wherein each of the plurality of stages includes:
a first circuit portion configured to operate in response to a previous carry signal; and
a first buffer portion controlled by the first circuit portion to output a corresponding scan signal of the plurality of scan signals and a corresponding sensing signal of a plurality of sensing signals,
wherein the dummy stage includes:
a second circuit portion configured to operate in response to the scan start signal; and
a second buffer portion configured to be controlled by the second circuit portion,
wherein a width of the second circuit portion of the dummy stage is narrower than a width of the first circuit portion of each of the plurality of stages, and
wherein a width of the second buffer portion of the dummy stage is narrower than a width of the first buffer portion of each of the plurality of stages.

11. The display panel of claim 10 , wherein the first circuit portion includes a sensing block configured to control an internal control node based on a sensing on signal and a sensing clock signal, and
wherein the second circuit portion does not include the sensing block.

12. The display panel of claim 10 , wherein a size of at least one transistor included in the second buffer portion is smaller than a size of at least one transistor included in the first buffer portion.

13. The display panel of claim 10 , wherein the first buffer portion includes a sensing signal outputting block configured to generate the corresponding sensing signal in response to a voltage of an internal control node of the first circuit portion, and
wherein the second circuit portion does not include the sensing signal outputting block.

14. The display panel of claim 1 , further comprising:
a wiring formed on the dummy stage and the plurality of stages,
wherein the wiring is spaced apart by a third distance from the pixel region, and is spaced apart by a fourth distance greater than the third distance from the open/short test region.

15. The display panel of claim 14 , wherein the wiring includes:
a first portion passing through the dummy stage and extending in a vertical direction;
a second portion extending in a horizontal direction between the dummy stage and the plurality of stages; and
a third portion passing through the plurality of stages and extending in the vertical direction.

16. A display device comprising:
a display panel including a pixel region comprising a plurality of pixels, an open/short test region comprising a plurality of open/short test pads, a dummy stage configured to generate a carry signal in response to a scan start signal, and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal;
a data driver configured to output data signals to the display panel; and
a controller configured to control the data driver, the dummy stage and the plurality of stages, wherein the plurality of stages is spaced apart by a first distance from the pixel region, and the dummy stage is spaced apart by a second distance greater than the first distance from the open/short test region.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Jun Hyun
• Kim Dong Woo
• Lee An Su
• Jo Kang Moon

Classifications

• G01R31/56

  Testing of electric apparatus (testing of transformers G01R31/62; testing of connections G01R31/66) · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title