Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

Patent metadata

Field	Value
Publication number	US-11196422-B2
Application number	US-201916968339-A
Country	US
Kind code	B2
Filing date	Feb 8, 2019
Priority date	Feb 9, 2018
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled.

First claim

The invention claimed is:

1. A battery-indifferent or pure energy harvesting multi-mode system comprising:
one or more cell logic structures each comprising:
a CMOS gate circuit;
a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and
a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage;

wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled;
an energy harvesting circuit for generating power for the multi-mode system; and
a power management circuit for switching between the different operation modes of the multi-mode system.

2. The multi-mode system of claim 1 , wherein the power management circuit comprises a self-startup circuit portion for gradually powering up the multi-mode system after an outage of power generated by the harvesting circuit.

3. The multi-mode system of claim 2 , wherein the self-startup circuit portion is configured to sequentially power up partitions of the multi-mode system.

4. The multi-mode system of claim 3 , wherein the self-startup circuit portion comprises a delay circuit for introducing a delay between power up of the respective partitions.

5. The multi-mode system of claim 1 , further comprising a battery configured to be recharged from the energy harvesting circuit, and, in one operation mode, power is provided to the multi-mode system at least partially by the battery, and in another operation mode, power is provided by the energy harvesting circuit only.

6. The multi-mode system of claim 1 , wherein in all operation modes of power is provided purely by different output levels of the energy harvesting circuit.

7. The multi-mode system of claim 1 , wherein the first and second header transistors comprise NMOS transistors.

8. The multi-mode system of claim 1 , wherein the first and second footer transistors comprise PMOS transistors.

9. The multi-mode system of claim 1 , wherein the header and footer circuits are configured for disabling the feedback by overdriving the gates of the first header transistor and the first footer transistor.

10. A method of operating a battery-indifferent or pure energy harvesting multi-mode system comprising the steps of:
controlling a header circuit coupled to a CMOS gate circuit, the header circuit comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit, and
controlling a footer circuit coupled to the CMOS gate circuit, the footer circuit comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage, such that the multi-mode system is switchable between different operation modes, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled;
generating power for the multi-mode system using an energy harvesting circuit; and
switching between the different operation modes of the multi-mode system.

11. The method of claim 10 , comprising gradually powering up the multi-mode system after an outage of power generated by the harvesting circuit.

12. The method of claim 11 , comprising sequentially powering up partitions of the dual-mode system.

13. The method of claim 12 , comprising introducing a delay between power up of the respective partitions.

14. The method of claim 10 , further comprising recharging a battery from the energy harvesting circuit, and, in one operation mode, power is provided to the multi-mode system at least partially by the battery, and in another operation mode, power is provided by the energy harvesting circuit only.

15. The method of claim 10 , wherein in all operation modes of power is provided purely by different output levels of the energy harvesting circuit.

16. The method of claim 10 , wherein the first and second header transistors comprise NMOS transistors.

17. The method of claim 10 , wherein the first and second footer transistors comprise PMOS transistors.

18. The method of claim 10 , comprising controlling the header and footer circuits for disabling the feedback by overdriving the gates of the first header transistor and the first footer transistor.

Assignees

• Nat Univ Singapore

Inventors

• Lin Longyang
• Jain Saurabh
• Alioto Massimo

Classifications

• H03K19/0185 Primary

  using field effect transistors only · CPC title

• H03K19/0948 Primary

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K17/161

  in field-effect transistor switches · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title