Laser diode current driving apparatus

US11196229B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11196229-B2
Application numberUS-201916440619-A
CountryUS
Kind codeB2
Filing dateJun 13, 2019
Priority dateJun 21, 2018
Publication dateDec 7, 2021
Grant dateDec 7, 2021

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A driver circuit for a laser diode is configured to pass a current. The circuit includes a charge-pump configured to generate an output boosted positive supply rail voltage. At least one switch is configured to couple the output of the charge-pump to a terminal of the laser diode and to isolate the positive supply rail from the terminal of the laser diode when the charge-pump is enabled.

First claim

Opening claim text (preview).

What is claimed is: 1. A driver circuit for a laser diode configured to pass a current, the driver circuit comprising: a drive transistor configured to supply the laser diode with a controllable current; a regulator configured to control the drive transistor, wherein the regulator comprises an input for indicating a controllable current target value and a forward biased modeled voltage generator configured to model the laser diode; a charge-pump configured to generate an output boosted positive supply rail voltage; a first switch circuit configured to couple the output of the charge-pump to the regulator in response to the charge-pump being enabled and couple the positive supply rail to the regulator in response to the charge-pump being disabled; and a second switch circuit configured to couple the output of the charge-pump to a terminal of the laser diode and to isolate the positive supply rail from the terminal of the laser diode in response to the charge-pump being enabled. 2. The driver circuit as claimed in claim 1 , wherein the second switch circuit is further configured to isolate the output of the charge-pump from the terminal of the laser diode and to couple the positive supply rail to the terminal of the laser diode in response to the charge-pump being disabled. 3. The driver circuit as claimed in claim 1 , further comprising a charge-pump regulator voltage generator configured to supply an input voltage to the charge-pump, wherein the charge-pump regulator voltage generator comprises one of a static charge-pump regulator voltage generator or a dynamic charge-pump regulator voltage generator. 4. The driver circuit as claimed in claim 3 , wherein the dynamic charge-pump regulator voltage generator comprises: a comparator configured to compare a portion of a controllable current target value and a further forward biased modeled voltage generator configured to model the laser diode; and a further switch circuit configured to couple the output of the charge-pump to the further forward biased modeled voltage generator in response to the charge-pump being enabled and couple the positive supply rail to the further forward biased modeled modelled voltage generator in response to the charge-pump being disabled. 5. The driver circuit as claimed in claim 1 , wherein the second switch circuit comprises a single switch. 6. The driver circuit as claimed in claim 1 , wherein the second switch circuit comprises a bulk switch. 7. The driver circuit as claimed in claim 6 , wherein the bulk switch comprises: an inverter configured to receive a charge-pump enable signal and configured to output an inverted charge-pump enable signal; a first PMOS transistor configured with a gate node coupled to the inverted charge-pump enable signal, a source node coupled to a charge-pump output and a bulk node and drain node coupled to a bulk switch output; a second PMOS transistor configured with a source node coupled to a lower voltage input and a bulk node and drain node coupled to the bulk switch output; a third PMOS transistor configured with a drain node coupled to a gate node of the second PMOS transistor, a source node coupled to the charge-pump output, a bulk node coupled to the bulk switch output and a gate node coupled to the inverted charge-pump enable signal; and a NMOS transistor configured with a drain node coupled to the gate node of the second PMOS transistor, a source node and a bulk node coupled to a ground node and a gate node coupled to the inverted charge-pump enable signal. 8. A range detector comprising: a laser diode; a charge-pump configured to generate an output boosted positive supply rail voltage; a switch circuit configured to couple the output of the charge-pump to a terminal of the laser diode and to isolate the positive supply rail from the terminal of the laser diode in response to the charge-pump being enabled; clocking circuitry; a first state machine circuit configured to confirm operations of the clocking circuitry; a second state machine circuit configured to confirm operations of the charge-pump and switch circuit; and a third state machine circuit configured to confirm the operations of the charge-pump, wherein the operations of the third state machine circuit are initialized by the operations of the second state machine circuit. 9. The range detector as claimed in claim 8 , wherein the switch circuit is further configured to isolate the output of the charge-pump from the terminal of the laser diode and to couple the positive supply rail to the terminal of the laser diode in response to the charge-pump being disabled. 10. The range detector as claimed in claim 8 , further comprising: a drive transistor configured to supply the laser diode with a controllable current; a regulator configured to control the drive transistor, wherein the regulator comprises an input for indicating a controllable current target value and a forward biased modeled voltage generator configured to model the laser diode; and a further switch circuit configured to couple the output of the charge-pump to the regulator in response to the charge-pump being enabled and couple the positive supply rail to the regulator in response to the charge-pump being disabled. 11. The range detector as claimed in claim 8 , further comprising a charge-pump regulator voltage generator configured to supply an input voltage to the charge-pump, wherein the charge-pump regulator voltage generator comprises one of a static charge-pump regulator voltage generator or a dynamic charge-pump regulator voltage generator. 12. The range detector as claimed in claim 11 , wherein the dynamic charge-pump regulator voltage generator comprises: a comparator configured to compare a portion of a controllable current target value and a further forward biased modeled voltage generator configured to model the laser diode; and a further switch circuit configured to couple the output of the charge-pump to the further forward biased modeled voltage generator in response to the charge-pump being enabled and couple the positive supply rail to the further forward biased modeled voltage generator in response to the charge-pump being disabled. 13. The range detector of claim 8 , wherein the switch circuit comprises a bulk switch comprising: an inverter configured to receive a charge-pump enable signal and configured to output an inverted charge-pump enable signal; a first PMOS transistor configured with a gate node coupled to the inverted charge-pump enable signal, a source node coupled to a charge-pump output and a bulk node and drain node coupled to a bulk switch output; a second PMOS transistor configured with a source node coupled to a lower voltage input and a bulk node and drain node coupled to the bulk switch output; a third PMOS transistor configured with a drain node coupled to a gate node of the second PMOS transistor, a source node coupled to the charge-pump output, a bulk node coupled to the bulk switch output and a gate node coupled to the inverted charge-pump enable signal; and a NMOS transistor configured with a drain node coupled to the gate node of the second PMOS transistor, a source node and a bulk node coupled to a ground node and a gate node coupled to the inverted charge-pump enable signal. 14. A method for driving a laser diode, the method comprising: supplying the laser diode with a controllable current using a drive transistor; controlling the drive transistor with a regulator configured to receive a controllable current target value; enabling a charge-pump to generate an output boosted positive supply rail voltage; coupling the output

Assignees

Inventors

Classifications

  • Stabilising during pulse modulation or generation · CPC title

  • using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • Protecting the laser, e.g. during switch-on/off, detection of malfunctioning or degradation · CPC title

  • having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] · CPC title

  • Systems determining position data of a target · CPC title

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Frequently asked questions

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What does patent US11196229B2 cover?
A driver circuit for a laser diode is configured to pass a current. The circuit includes a charge-pump configured to generate an output boosted positive supply rail voltage. At least one switch is configured to couple the output of the charge-pump to a terminal of the laser diode and to isolate the positive supply rail from the terminal of the laser diode when the charge-pump is enabled.
Who is the assignee on this patent?
St Microelectronics Res & Dev Ltd
What technology area does this patent fall under?
Primary CPC classification H01S5/06835. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).