Array substrate and flexible display panel

US11195859B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11195859-B2
Application numberUS-202016770769-A
CountryUS
Kind codeB2
Filing dateFeb 13, 2020
Priority dateDec 10, 2019
Publication dateDec 7, 2021
Grant dateDec 7, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An array substrate and a flexible display panel are provided. The array substrate is in a bending region and includes a base; an inorganic layer formed on the base, wherein at least one hollowing-out region is disposed in the inorganic layer, and the hollowing-out region is non-filled or filled with an organic matter; and a metal layer formed on the inorganic layer and connected to layers on a bottom of the inorganic layer by at least one via hole encircled by the at least one hollowing-out region. When the flexible display panel is bent, the at least one hollowing-out region provides a good channel for releasing stress in the inorganic layer and improves the bending performance of the flexible display panel.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, wherein the array substrate is in a bending region and comprises: a base; an inorganic layer formed on the base, wherein at least one hollowing-out region is disposed in the inorganic layer, and the hollowing-out region is non-filled or filled with an organic matter; and a metal layer formed on the inorganic layer and connected to layers on a bottom of the inorganic layer by at least one via hole encircled by the at least one hollowing-out region; wherein the inorganic layer comprises at least two layers, wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer is any layer of a first gate insulating layer, a second gate insulating layer, or an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 2. The array substrate as claimed in claim 1 , wherein the inorganic layer comprises any two of a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, and the metal layer is a source/drain electrode layer. 3. The array substrate as claimed in claim 2 , wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer comprises any two of a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 4. The array substrate as claimed in claim 2 , wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer comprises a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 5. The array substrate as claimed in claim 1 , wherein the inorganic layer comprises a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, and the metal layer is a source/drain electrode layer. 6. A flexible display panel, comprising an array substrate, wherein the array substrate is in a bending region and comprises: a base; an inorganic layer formed on the base, wherein at least one hollowing-out region is disposed in the inorganic layer, and the hollowing-out region is non-filled or filled with an organic matter; and a metal layer formed on the inorganic layer and connected to layers on a bottom of the inorganic layer by at least one via hole encircled by the at least one hollowing-out region; wherein the inorganic layer comprises at least two layers, wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer is any layer of a first gate insulating layer, a second gate insulating layer, or an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 7. The flexible display panel as claimed in claim 6 , wherein the inorganic layer comprises any two of a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, and the metal layer is a source/drain electrode layer. 8. The flexible display panel as claimed in claim 7 , wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer comprises any two of a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 9. The flexible display panel as claimed in claim 7 , wherein the inorganic layer comprises a first inorganic layer and a second inorganic layer, the metal layer comprises a first metal layer and a second metal layer, the first metal layer, the second inorganic layer, and the second metal layer are sequentially formed on the first inorganic layer, the first inorganic layer comprises a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, the first metal layer is a source/drain electrode layer, the second inorganic layer is a passivation layer, and the second metal layer is a pixel electrode layer. 10. The flexible display panel as claimed in claim 6 , wherein the inorganic layer comprises a first gate insulating layer, a second gate insulating layer, and an interlayer insulation layer, and the metal layer is a source/drain electrode layer.

Assignees

Inventors

Classifications

  • characterised by the compositions or shapes of the interlayer dielectrics · CPC title

  • Interconnections, e.g. scanning lines · CPC title

  • H10D86/411Primary

    characterised by materials, geometry or structure of the substrates · CPC title

  • H10D86/60Primary

    wherein the TFTs are in active matrices · CPC title

  • the display being formed by a plurality of foldable display components (G06F1/1647 takes precedence) · CPC title

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What does patent US11195859B2 cover?
An array substrate and a flexible display panel are provided. The array substrate is in a bending region and includes a base; an inorganic layer formed on the base, wherein at least one hollowing-out region is disposed in the inorganic layer, and the hollowing-out region is non-filled or filled with an organic matter; and a metal layer formed on the inorganic layer and connected to layers on a …
Who is the assignee on this patent?
Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).