Display panel including demultiplexer, method of driving the same and display device

Patent metadata

Field	Value
Publication number	US-11195484-B2
Application number	US-202017041357-A
Country	US
Kind code	B2
Filing date	Apr 16, 2020
Priority date	Apr 18, 2019
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

The present disclosure provides a display panel, a method of driving the display panel and a display device. Each signal input sub-circuitry of the display panel includes at least two transistors. A same control signal is applied to control signal lines corresponding to a same signal input sub-circuitry, different control signals are applied to control signal lines corresponding to different signal input sub-circuitries, and time periods within which the different control signals are at active levels are staggered from each other. A sum of width-to-length ratios of channels of the at least two transistors is equal to a first predetermined value, and an overlapping area of the gate electrode of each of the at least two transistors relative to an active layer of the transistor is smaller than a second predetermined value in a direction perpendicular to a base substrate of the display panel.

First claim

What is claimed is:

1. A display panel, comprising a plurality of signal input circuitries, wherein at least one of the plurality of signal input circuitries comprises:
a signal transmission line, a plurality of control signal lines, a plurality of data signal lines and a plurality of signal input sub-circuitries in one-to-one correspondence with the plurality of data signal lines,
wherein: each signal input sub-circuitry comprises at least two transistors, input electrodes of which are coupled to the signal transmission line, output electrodes of which are coupled to a corresponding data signal line, and gate electrodes of which are coupled to the plurality of control signal lines in one-to-one correspondence;
a same control signal is appliable to the control signal lines corresponding to a same signal input sub-circuitry, different control signals are appliable to the control signal lines corresponding to different signal input sub-circuitries, and time periods within which the different control signals are at active levels are staggered from each other; and
a sum of width-to-length ratios of channels of the at least two transistors is equal to a first predetermined value, and an overlapping area of the gate electrode of each of the at least two transistors relative to an active layer of the transistor is smaller than a second predetermined value in a direction perpendicular to a base substrate of the display panel; and
wherein the first predetermined value is a width-to-length ratio of a channel of one transistor when each signal input sub-circuitry comprises the transistor in a one-to-one correspondence with the data signal line, and the second predetermined value is an overlapping area of a gate electrode of one transistor relative to an active layer of the transistor when each signal input sub-circuitry comprises the transistor in a one-to-one correspondence with the data signal line.

2. The display panel according to claim 1 , wherein a sum of the overlapping areas of the gate electrodes of the at least two transistors relative to the active layers of the at least two transistors is equal to the second predetermined value in the direction perpendicular to the base substrate.

3. The display panel according to claim 1 , wherein the plurality of signal input sub-circuitries are arranged sequentially in a direction perpendicular to an extension direction of the data signal line, and wherein each signal input sub-circuitry comprises two transistors arranged sequentially in the extension direction of the data signal line, input electrodes of the two transistors are coupled to each other, output electrodes of the two transistors are coupled to each other, the input electrode of one of the two transistors is coupled to the signal transmission line, and the output electrode of the other one of the two transistors is coupled to the corresponding data signal line.

4. The display panel according to claim 3 , wherein two control signal lines corresponding to the two transistors are arranged opposite to each other, and the two transistors are arranged between the two control signal lines.

5. The display panel according to claim 3 , wherein the active layer of each transistor comprises at least two active patterns independent of each other, and an orthogonal projection of each active pattern onto the base substrate partially overlaps an orthogonal projection of the gate electrode of the transistor onto the base substrate, an orthogonal projection of the input electrode of the transistor onto the base substrate, and an orthogonal projection of the output electrode of the transistor onto the base substrate.

6. The display panel according to claim 3 , wherein each signal input circuitry comprises at least two signal input sub-circuitries, each of the at least two signal input sub-circuitries is configured to transmit a color data signal from the signal transmission line to a corresponding data signal line, and the data signal line is configured to transmit the color data signal to subpixel units of the display panel corresponding to the data signal line, and wherein each signal input sub-circuitry is further configured to transmit color data signals for different colors to the corresponding subpixel units via the data signal lines, and the subpixels in different colors corresponding to the at least two signal input sub-circuitries achieve color display.

7. The display panel according to claim 6 , wherein each signal input circuitry comprises a first signal input sub-circuitry, a second signal input sub-circuitry and a third signal input sub-circuitry; the first signal input sub-circuitry is configured to transmit a first color data signal from the signal transmission line to a corresponding data signal line, and the data signal line is configured to transmit the first color data signal to subpixel units of the display panel in a first color corresponding to the data signal line; the second signal input sub-circuitry is configured to transmit a second color data signal from the signal transmission line to a corresponding data signal line, and the data signal line is configured to transmit the second color data signal to subpixel units of the display panel in a second color corresponding to the data signal line; the third signal input sub-circuitry is configured to transmit a third color data signal from the signal transmission line to a corresponding data signal line, and the data signal line is configured to transmit the third color data signal to subpixel units of the display panel in a third color corresponding to the data signal line; and each of the first color, the second color and the third color is one of red, green and blue respectively.

8. The display panel according to claim 7 , wherein the first signal input sub-circuitry, the second signal input sub-circuitry and the third signal input sub-circuitry are arranged sequentially in the direction perpendicular to the extension direction of the data signal line; the data signal line comprises a first data signal sub-line corresponding to the first signal input sub-circuitry, a second data signal sub-line corresponding to the second signal input sub-circuitry, and a third data signal sub-line corresponding to the third signal input sub-circuitry; the signal transmission line comprises a first signal transmission sub-line corresponding to the first signal input sub-circuitry, a second signal transmission sub-line corresponding to the second signal input sub-circuitry, and a third signal transmission sub-line corresponding to the third signal input sub-circuitry; the control signal line comprises a first control signal sub-line and a second control signal sub-line corresponding to the first signal input sub-circuitry, a third control signal sub-line and a fourth control signal sub-line corresponding to the second signal input sub-circuitry, and a fifth control signal sub-line and a sixth control signal sub-line corresponding to the third signal input sub-circuitry; the first signal input sub-circuitry comprises a first transistor and a second transistor arranged sequentially in the extension direction of the data signal line, input electrodes of the first transistor and the second transistor are coupled to each other, output electrodes of the first transistor and the second transistor are coupled to each other, the input electrode of the first transistor is coupled to the first signal transmission sub-line, the output electrode of the second transistor is coupled to the first data signal sub-line, a gate electrode of the first transistor is coupled to the first control signal sub-line, and a gate electrode of the second transistor is coupled to the second control signal sub-line; the second signal input sub-circuitry comprises a third tr

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Li Lei
• Fan Jun
• Ta Le
• Liu Yusheng
• Zhang Yongqiang
• Li Mei
• Li Yafei
• Liu Peng
• Guo Zhixuan

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• G09G3/3607 Primary

  for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127) · CPC title

• G02F1/13452

  Conductors connecting driver circuitry and terminals of panels · CPC title