Storage devices hiding parity swapping behavior

US11194494B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11194494-B2
Application numberUS-202016858358-A
CountryUS
Kind codeB2
Filing dateApr 24, 2020
Priority dateApr 24, 2020
Publication dateDec 7, 2021
Grant dateDec 7, 2021

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage device, comprising: a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of streams, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks; a first volatile memory unit; and a controller coupled to the non-volatile storage unit and the first volatile memory unit, the controller comprising a second volatile memory unit, wherein the controller is configured to: set a minimum write size for commands to write data received from a host device; receive one or more commands to write data in the minimum write size to one or more streams of the plurality of streams; generate new first parity data for a first stream of the plurality of streams in a temporary location in the second volatile memory unit; copy previous first parity data for the first stream from the first volatile memory unit to a first location in the second volatile memory unit; and update the previous first parity data with the new first parity data in the second volatile memory unit. 2. The storage device of claim 1 , wherein the previous first parity data is updated with the new first parity data in the first location in the second volatile memory unit. 3. The storage device of claim 1 , wherein the previous first parity data is updated with the new first parity data in the temporary location in the second volatile memory unit. 4. The storage device of claim 1 , wherein the minimum write size is based on a program time of writing the data associated with the one or more commands to the one or more streams. 5. The storage device of claim 1 , wherein the minimum write size is based on a transfer speed for copying the previous first parity data from the first volatile memory unit to the second volatile memory unit. 6. The storage device of claim 1 , wherein the minimum write size is based on an amount of time it takes to generate the new first parity data. 7. The storage device of claim 1 , wherein the controller is further configured to: copy the updated first parity data from the second volatile memory unit to the first volatile memory unit; and erase the temporary location in the second volatile memory unit after the previous first parity data is updated with the new first parity data. 8. A storage device, comprising: a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of streams, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks; a first volatile memory unit; and a controller coupled to the non-volatile storage unit and the first volatile memory unit, the controller comprising a second volatile memory unit, wherein the controller is configured to: receive a first command to write data in a minimum write size to a first stream of the plurality of streams; simultaneously, generate new first parity data for the first stream in a temporary location in the second volatile memory unit, the new first parity data being associated with the first command, write the data associated with the first command to the first stream, and copy previous first parity data for the first stream from the first volatile memory unit to a first location in the second volatile memory unit; update the previous first parity data with the new first parity data in the first location in the second volatile memory unit; erase the temporary location in the second volatile memory unit; receive a second command to write data in the minimum write size to a second stream; simultaneously, generate new second parity data for the second stream in the temporary location in the second volatile memory unit, the new second parity data being associated with the second command, write the data associated with the second command to the second stream, and copy previous second parity data for the second stream from the first volatile memory unit to a second location in the second volatile memory unit; and update the previous second parity data with the new second parity data in the temporary location in the second volatile memory unit. 9. The storage device of claim 8 , wherein the controller is further configured to copy the updated first parity data from the second volatile memory unit to the first volatile memory unit after updating the previous first parity data with the new first parity data. 10. The storage device of claim 8 , wherein the controller is further configured to copy the updated second parity data from the second volatile memory unit to the first volatile memory unit after updating the previous second parity data with the new second parity data. 11. The storage device of claim 8 , wherein the minimum write size is selected by the storage device to match a program time of writing the data associated with the one or more commands to the plurality of streams to a transfer speed for copying previous parity data from the first volatile memory unit to the second volatile memory unit. 12. The storage device of claim 11 , wherein the minimum write size is about 1 MiB or greater. 13. The storage device of claim 8 , wherein the controller comprises an XOR engine configured to generate the first parity data and update the second parity data. 14. The storage device of claim 8 , wherein the first volatile memory unit is a DRAM unit, and wherein the second volatile memory unit is a SRAM unit. 15. A storage device, comprising: a non-volatile storage unit, wherein a capacity of the non-volatile storage unit is divided into a plurality of streams, and wherein the non-volatile storage unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks; a DRAM unit; and a controller coupled to the non-volatile storage unit and the DRAM unit, the controller comprising a SRAM unit, wherein the controller is configured to: receive one or more commands to write data to one or more streams of the plurality of streams, wherein the data associated with the one or more commands are restricted to a minimum write size; generate new first parity data for a first stream in a temporary location in the SRAM unit, the new first parity data being associated with a first command received in the minimum write size, and write the data associated with the first command to the first stream simultaneously; erase a first location in the SRAM unit; copy previous first parity data for the first stream from the DRAM unit to the first location in the SRAM unit; combine the previous first parity data with the new first parity data in the SRAM unit; and copy the combined first parity data from the SRAM unit to a first location in the DRAM unit, wherein the minimum write size is rate matched to a program time of writing the data associated with the one or more commands to the one or more streams, a transfer speed for copying previous parity data from the DRAM unit to the SRAM unit, or an amount of time it takes to generate new parity data. 16. The storage device of claim 15 , wherein the minimum write size is about 1 MiB or greater. 17. The storage device of claim 15 , wherein the minimum write size is further based on an amount of time it takes to generate the new first parity data. 18. The storage device of claim 15 , wherein the controller is further configure to calculate and determine the minimum write size for commands to write data received from a host device. 1

Assignees

Inventors

Classifications

  • using arrangements adapted for a specific error detection or correction feature · CPC title

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • in relation to data integrity, e.g. data losses, bit errors · CPC title

  • Data buffering arrangements · CPC title

  • G06F3/064Primary

    Management of blocks · CPC title

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What does patent US11194494B2 cover?
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A t…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0659. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).