Receiving device, receiving method, and receiving system

Patent metadata

Field	Value
Publication number	US-11190263-B2
Application number	US-202017031384-A
Country	US
Kind code	B2
Filing date	Sep 24, 2020
Priority date	Mar 29, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A receiving device includes an equalization processor including multiple delay equalizers. The equalization processor is configured to: obtain a first error between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized; cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.

First claim

The invention claimed is:

1. A receiving device comprising:
an equalization processor which comprises multiple delay equalizers that respectively receive multiple reception signals through an array antenna, and which performs equalization processing of spatial equalization and temporal equalization on the reception signals,
wherein the equalization processor is configured to:
obtain a first error which is a difference between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized;
cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error which is a difference between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and
update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.

2. The receiving device according to claim 1 ,
wherein each of the multiple delay equalizers has N taps of a first tap to an n-th tap, where N indicates an integer greater than or equal to 2, and
wherein the equalization processor is configured to:
specify the specific tap among the N taps as a tap for performing spatial equalization, calculate the first weight based on an output of the specific tap in the multiple delay equalizers, and update a coefficient of the specific tap,
in a state where an update amount of the specific tap is reflected in the first tap to the n-th tap except the specific tap, calculate a second weight based on outputs of the N taps of the first tap to the n-th tap, and update coefficients of the first tap to the n-th tap except the specific tap, and
update the coefficient of the specific tap based on the first weight and the coefficients of the first tap to the n-th tap except the specific tap based on the second weight at the same update timing.

3. The receiving device according to claim 2 ,
wherein each of the multiple delay equalizers comprises N−1 delay elements and N complex multipliers of the first tap to the n-th tap connected to input sides and output sides of the N−1 delay elements.

4. The receiving device according to claim 3 ,
wherein the equalization processor comprises:
a first combiner configured to combine outputs of the complex multipliers of the specific tap of the multiple delay equalizers;
a first adder configured to output, as the first error, a difference between an output of the first combiner and the reference value;
a first weight calculator configured to calculate the first weight based on the first error output from the first adder and update the first weight to update the coefficient of the specific tap.

5. The receiving device according to claim 4 ,
wherein the equalization processor calculates the update amount of the specific tap based on a first weight before update and a first weight after update.

6. The receiving device according to claim 5 ,
wherein the equalization processor reflects the update amount of the specific tap in the first tap to the n-th tap except the specific tap by multiplying weights of the first tap to the n-th tap except the specific tap by the update amount of the specific tap.

7. The receiving device according to claim 6 ,
wherein the equalization processor further comprises:
a second combiner configured to combine outputs of the complex multipliers of the N taps of the multiple delay equalizers;
a second adder configured to output, as the second error, a difference between an output of the second combiner and the reference value;
a second weight calculator configured to calculate the second weight based on the second error output from the second adder and update the second weight to update the coefficients of the first tap to the n-th tap except the specific tap.

8. The receiving device according to claim 1 ,
wherein the same timing is the same frame as a time unit.

9. A receiving system, comprising:
a reception signal input device which inputs a reception signal of a radio wave;
an equalization processor which performs equalization processing of the reception signal; and
a sound signal output device which outputs an equalized signal,
wherein the reception signal input device comprises:
an array antenna comprising multiple antennas that receive radio waves of a desired wave; and
front ends configured to perform frequency conversion of the received multiple signals, respectively,

wherein the sound signal output device comprises:
an output signal amplifier that amplifies the equalized signal; and
a sound output device that outputs an amplified signal as a sound signal, and

wherein the equalization processor comprises multiple delay equalizers that respectively receive multiple reception signals, and performs equalization processing of spatial equalization and temporal equalization on the reception signals, the equalization processor being configured to:
obtain a first error which is a difference between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized;
cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error which is a difference between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and
update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.

10. The receiving system according to claim 9 ,
wherein each of the multiple delay equalizers has N taps of a first tap to an n-th tap, where N indicates an integer greater than or equal to 2, and
wherein the equalization processor is configured to:
specify the specific tap among the N taps as a tap for performing spatial equalization, calculate the first weight based on an output of the specific tap in the multiple delay equalizers, and update a coefficient of the specific tap,
in a state where an update amount of the specific tap is reflected in the first tap to the n-th tap except the specific tap, calculate a second weight based on outputs of the N taps of the first tap to the n-th tap, and update coefficients of the first tap to the n-th tap except the specific tap, and
update the coefficient of the specific tap based on the first weight and the coefficients of the first tap to the n-th tap except the specific tap based on the second weight at the same timing.

11. The receiving system according to claim 10 ,
wherein each of the multiple delay equalizers comprises N−1 delay elements and N complex multipliers of the first tap to the n-th tap connected to input sides and output sides of the N−1 delay elements.

12. The receiving system according to claim 11 ,
wherein the equalization processor comprises:
a first combiner configured to combine outputs of the complex multipliers of the specific tap of the multiple delay equalizers;
a first adder configured to output, as the first error, a difference between an output of the first combiner and the reference value;
a first weight calculator configured to calculates the fir

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Asada Yohei
• SHINDO Ryohei

Classifications

• H04B7/0845 Primary

  per branch equalization, e.g. by an FIR-filter or RAKE receiver per antenna branch (rake receivers as such H04B1/7115) · CPC title

• H04B1/76

  Pilot transmitters or receivers for control of transmission or for equalising · CPC title

• H04B7/0828

  with delay elements in antenna paths · CPC title

• H04B1/71057

  using maximum-likelihood sequence estimation [MLSE] · CPC title

• H04L25/03891

  Spatial equalizers (MIMO diversity systems H04B7/0413) · CPC title