Array substrate and manufacturing method therefor, and display device

Patent metadata

Field	Value
Publication number	US-11189679-B2
Application number	US-201916711972-A
Country	US
Kind code	B2
Filing date	Dec 12, 2019
Priority date	Mar 29, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate and a plurality of pixel units disposed on the base substrate, wherein at least one pixel unit includes:
a plurality of thin film transistors including at least one first thin film transistor and a second thin film transistor, wherein the at least one first thin film transistor includes:
a first active pattern disposed above the base substrate;
a first gate disposed at a side of the first active pattern away from the base substrate; and
a first source and a first drain that are disposed at a side of the first gate away from the base substrate, wherein the first source and the first drain are coupled to the first active pattern;

and the second thin film transistor includes:
a second active pattern disposed in a same layer as the first active pattern;
a second source and a second drain that are disposed in a same layer as the first source and the first drain, wherein the second source and the second drain are coupled to the second active pattern, and
a second gate disposed in a same layer as the first gate;

a first electrode disposed in a same layer as the first active pattern, wherein the first electrode is coupled to the first drain;
a second electrode disposed in a same layer as the first gate, wherein the second electrode is coupled to the second drain, and
a third electrode disposed between the first electrode and the base substrate, wherein the third electrode is coupled to the second drain;
orthographic projections of any two in a group consisting of the third electrode, the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region, and the third electrode is coupled to the second electrode.

2. The array substrate according to claim 1 , wherein the at least one pixel unit further includes light-shielding patterns disposed in a same layer as the third electrode, and orthographic projections of the first active pattern and the second active pattern on the base substrate are located within an orthographic projection of the light-shielding patterns on the base substrate.

3. The array substrate according to claim 2 , wherein
a material of the first active pattern is an oxide semiconductor, and a material of the first electrode is an oxide conductor; and/or,
the first gate is made of a same material as the second electrode; and/or,
the light-shielding patterns are made of a same material as the third electrode, and a material of the light-shielding patterns is metal.

4. The array substrate according to claim 2 , wherein the third electrode and the light-shielding patterns are disposed on the base substrate, and the array substrate further comprises:
a buffer layer disposed between a layer where the third electrode and the light-shielding patterns are located, and a layer where the first active pattern, the second active pattern and the first electrode are located;
a gate insulating layer disposed between the layer where the first active pattern, the second active pattern and the first electrode are located, and a layer where the first gate, the second gate and the second electrode are located; and
an interlayer insulating layer disposed between the layer where the first gate, the second gate and the second electrode are located, and a layer where the first source, the first drain, the second source and the second drain are located,
wherein the at least one pixel unit further includes:
a first via hole extending through the interlayer insulating layer, wherein the second drain is coupled to the second electrode though the first via hole;
a second via hole extending through the interlayer insulating layer, the gate insulating layer, and the buffer layer, wherein the second drain is coupled to the third electrode through the second via hole; and
a third via hole extending through the interlayer insulating layer and the gate insulating layer, wherein the first drain is coupled to the first electrode through the third via hole.

5. The array substrate according to claim 4 , wherein the second via hole includes:
a first sub via hole extending through the interlayer insulating layer; and
a second sub via hole extending through the gate insulating layer and the buffer layer,
wherein the at least one pixel unit further includes a first interconnecting pattern disposed in a same layer as the second electrode, the second drain is coupled to the first interconnecting pattern through the first sub via hole, and the first interconnecting pattern is coupled to the third electrode though the second sub via hole.

6. The array substrate according to claim 4 , further compring sense lines disposed in a same layer as the second electrode, wherein the at least one pixel unit further includes:
a sixth via hole including a third sub via hole and a fourth sub via hole, wherein the third sub via hole extends through the interlayer insulating layer, and the fourth sub via hole extends through the gate insulating layer and the buffer layer;
a seventh via hole including a fifth sub via hole and a sixth sub via hole, wherein the fifth sub via hole extends through the interlayer insulating layer, and the sixth sub via hole extends through the gate insulating layer and the buffer layer;
a second interconnecting pattern disposed in a same layer as the second electrode, wherein the second interconnecting pattern is coupled to the first source through the third sub via hole, and the second interconnecting pattern is coupled to one of the light-shielding patterns through the fourth sub via hole, wherein orthographic projections of the second interconnecting pattern and the one of the light-shielding patterns on the base substrate have an overlapping region; and
a third interconnecting pattern disposed in a same layer as the second electrode, wherein the third interconnecting pattern is coupled to one of the sense lines through the fifth sub via hole, and the third interconnecting pattern is coupled to the one of the light-shielding patterns through the sixth sub via hole.

7. The array substrate according to claim 4 , wherein the plurality of thin film transistors further includes a third thin film transistor, and the third thin film transistor includes:
a third active pattern disposed in a same layer as the first active pattern;
a third source and a third drain that are disposed in a same layer as the first source and the first drain, wherein the third source and the third drain are coupled to the third active pattern; and
a third gate disposed in a same layer as the first gate, wherein the third gate is coupled to the second electrode.

8. The array substrate according to claim 7 , wherein the at least one pixel unit further includes a pixel electrode disposed at a side of the third source and the third drain away from the base substrate, and the first drain and the third drain are coupled to the pixel electrode.

9. The array substrate according to claim 8 , further comprising a planarization layer disposed between a layer where the pixel electrode is located and a layer where the third source and the third drain are located, wherein the at least one pixel unit further includes:
a fourth via hole extending through the planarization layer, wherein the third drain is coupled to the pixel electrode through the fourth via hole; and
a fifth via hole extending through the planarization layer, wherein the first drain is coupled to the pixel electrode through the fifth via hole.

10. The array substrate according to claim 8 , wherein the at least one pixel unit further includes:
a light-emitting functional layer disposed above a surface of the pixel electrode away from the base substrate, and
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Assignees

• Boe Technology Group Co Ltd

Inventors

• Feng Jing
• Yin Dongsheng
• Ning ce
• Wang Jiushi

Classifications

• H01L27/3265

  Electricity · mapped topic

• H01L27/3272

  Electricity · mapped topic

• H01L27/3262 Primary

  Electricity · mapped topic

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title