Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements

Patent metadata

Field	Value
Publication number	US-11189564-B2
Application number	US-201815943541-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a source electrode in contact with a source area on a substrate;
a drain electrode in contact with a drain area on the substrate;
a channel area including a first channel region next to the source area, and a second channel region next to the drain area, wherein the first channel region includes a dopant of a first concentration, and the second channel region includes the dopant of a second concentration higher than the first concentration;
a gate oxide layer above the channel area; and
a gate electrode above the gate oxide layer;
wherein the source area, the channel area, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), a first resistance exists between the source electrode and the gate electrode, and wherein a second resistance exists between the source electrode and the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode, after a programming operation is performed when a programming voltage is applied to the gate electrode and the source electrode is coupled to a ground voltage to generate a current between the source electrode, the gate oxide layer, and the gate electrode.

2. The integrated circuit of claim 1 , wherein the programming operation is performed after a forming operation has been performed, and wherein when the forming operation is performed, the programming voltage is applied to the gate electrode and the drain electrode, and the source electrode is coupled to the ground voltage.

3. The integrated circuit of claim 1 , wherein the programming operation is performed when the programming voltage is applied to the drain electrode.

4. The integrated circuit of claim 1 , wherein the substrate is a bulk substrate or a silicon-on-insulator (SOI) substrate.

5. The integrated circuit of claim 1 , wherein the MOSFET is a PMOS MOSFET or a NMOS MOSFET.

6. The integrated circuit of claim 1 , wherein the programming voltage is less than about 2.5V between the gate electrode and the source electrode.

7. The integrated circuit of claim 1 , wherein the current is less than about 100 μA.

8. The integrated circuit of claim 1 , wherein the first resistance is about 10 2 to 10 6 times larger than the second resistance.

9. The integrated circuit of claim 1 , wherein the first concentration of the dopant is in a range of about 10 15 cm −3 to about 10 16 cm −3 , and the second concentration of the dopant is in a range of 10 17 cm −3 to about 10 18 cm −3 .

10. The integrated circuit of claim 1 , wherein the dopant includes Silicon (Si), Germanium (Ge), Carbon (C), or Boron (B).

11. The integrated circuit of claim 1 , wherein the dopant is distributed in a graded pattern, or uniformed distributed in the second channel region.

12. The integrated circuit of claim 1 , wherein the source electrode, the drain electrode, or the gate electrode includes polycrystalline silicon (poly-Si), polycrystalline silicon-germanium, germanium (Ge), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

13. The integrated circuit of claim 1 , further comprising:
a first selector coupled to the drain electrode; and
a second selector coupled to the source electrode.

14. The integrated circuit of claim 13 , wherein the first selector or the second selector is a PMOS transistor or a NMOS transistor.

15. A method for forming an integrated circuit, the method comprising:
forming a source area on a substrate, and a drain area on the substrate;
forming a channel area including a first channel region next to the source area, wherein the first channel region includes a dopant of a first concentration;
forming a second channel region of the channel area next to the drain area, wherein the second channel region includes the dopant of a second concentration higher than the first concentration;
forming a gate oxide layer above the channel area; and
forming a gate electrode above the channel area and above the substrate, a source electrode in contact with the source area, and a drain electrode in contact with the drain area, wherein the source area, the channel area, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), a first resistance exists between the source electrode and the gate electrode, and wherein a second resistance exists between the source electrode and the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode, after a programming operation is performed when a programming voltage is applied to the gate electrode and the source electrode is coupled to a ground voltage to generate a current between the source electrode, the gate oxide layer, and the gate electrode.

16. The method of claim 15 , wherein the programming operation is performed after a forming operation has been performed, and wherein when the forming operation is performed, the programming voltage is applied to the gate electrode and the drain electrode, and the source electrode is coupled to the ground voltage.

17. The method of claim 15 , wherein the programming voltage is less than about 2.5V between the gate electrode and the source electrode.

18. The method of claim 15 , wherein the first concentration of the dopant is in a range of about 10 15 cm −3 to about 10 16 cm −3 , and the second concentration of the dopant is in a range of 10 17 cm −3 to about 10 18 cm −3 .

19. The method of claim 15 , wherein the dopant includes Si, Ge, C, or Boron.

20. The method of claim 15 , wherein the first resistance is about 10 2 to 10 6 times larger than the second resistance.

21. A computing device, comprising:
a circuit board; and
an antifuse memory array coupled to the circuit board, wherein the antifuse memory array includes a plurality of antifuse cells, an antifuse cell of the plurality of antifuse cells includes an antifuse element coupled to a first selector and a second selector, and wherein the antifuse element includes:
a source electrode in contact with a source area on a substrate and coupled to a source line of the antifuse memory array through the first selector;
a drain electrode in contact with a drain area on the substrate and coupled to a word line of the antifuse memory array through the second selector;
a channel area including a first channel region next to the source area, and a second channel region next to the drain area, wherein the first channel region includes a dopant of a first concentration, and the second channel region includes the dopant of a second concentration higher than the first concentration;
a gate oxide layer above the channel area; and
a gate electrode above the gate oxide layer and coupled to a bit line of the antifuse memory array;

wherein the source area, the channel area, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), a first resistance exists between the source electrode and the gate electrode, and wherein a second resistance exists between the source electrode and the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode, after a programming operation is performed when a programming voltage is applied to the gate electr

Assignees

• Intel Corp

Inventors

• Chao Yu-Lin
• Kulkarni Sarvesh H
• Dorgan Vincent E
• Bhattacharya Uddalak

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title