Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

Patent metadata

Field	Value
Publication number	US-11189537-B2
Application number	US-201213425589-A
Country	US
Kind code	B2
Filing date	Mar 21, 2012
Priority date	Mar 21, 2012
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

First claim

What is claimed is:

1. A circuit package, comprising:
an electronic circuit;
one or more metal blocks next to the electronic circuit;
an encapsulation material between the electronic circuit and the metal block;
a first metal layer structure electrically contacted to at least one first contact pad on a first side of the electronic circuit;
a second metal layer structure electrically contacted to at least one second contact pad on a second side of the electronic circuit, wherein the second side is opposite to the first side;
a joining material between the at least one first contact pad on a first side of the electronic circuit and the first metal layer structure; and
an electrically conductive medium comprising a first electrically conductive medium electrically contacting the metal block to the first metal layer structure and a second electrically conductive medium electrically contacting the metal block to the second metal layer structure;
wherein the first metal layer structure and the second metal layer structure comprise a metallic element;
wherein the first electrically conductive medium comprises a first intermetallic phase material comprising a first metallic element that is a different element than the metallic element and the second electrically conductive medium comprises a second intermetallic phase material comprising a second metallic element that is a different element than the metallic element;
wherein the first metallic element is a different element than the second metallic element; and
wherein the electrically conductive medium and the joining material is a paste comprising one or more of nanoparticles, nanostructures, nanofibers, nanowires, graphene, and combinations thereof;
wherein the electrically conductive medium comprises at least one from the following group of materials, the group of materials consisting of: Ag—Sn, Cu—Sn, Cu—Sn—Ag, Au—Sn, Ni—Sn, Cu—Zn, Cu—Co, In—Sn, Pd—Sn, Au—Ag—Sn, Pd—Au—Sn, and combinations thereof; and
wherein the first electrically conductive medium is configured to change between a solid and a liquid at a first temperature, and wherein the second electrically conductive medium is configured to change between a solid and a liquid at a second temperature, different from the first temperature.

2. The circuit package of claim 1 ,
wherein the electrically conductive medium has a material structure different from the material of the metal block.

3. The circuit package of claim 1 ,
wherein
the first electrically conductive medium electrically contacts a first side of the metal block and the first metal layer structure; and
the second electrically conductive medium electrically contacts a second side of the metal block and the second metal layer structure.

4. The circuit package of claim 1 ,
wherein the one or more of nanoparticles, nanostructures, nanofibers, nanowires, graphene, and combinations thereof comprises at least one material from the following group of materials, the group consisting of: metals, metal oxides, silver, copper, carbon, and combinations thereof.

5. The circuit package of claim 1 ,
wherein the first metal layer structure is formed on the at least one first contact pad on the first side of the electronic circuit and over a first side of the metal block.

6. The circuit package of claim 1 ,
wherein the second metal layer structure is formed on the at least one second contact pad on the second side of the electronic circuit and over a second side of the metal block.

7. The circuit package of claim 1 ,
wherein the first metal layer structure and the second metal layer structure comprise a lead frame.

8. The circuit package of claim 1 ,
wherein the first metal layer structure and the second metal layer structure form a redistribution layer.

9. The circuit package of claim 1 ,
wherein the first metal layer structure and the second metal layer structure comprise at least one from the following group of materials, the group of materials consisting of: Cu, Au, Ag, Pd, Ni, Fe, Al, and combinations thereof.

10. The circuit package of claim 1 ,
wherein the metal block comprises at least one from the following group of materials, the group of materials consisting of: Cu, Au, Ag, Pd, Ni, Fe, Al, and combinations thereof.

11. The circuit package of claim 1 ,
wherein the electronic circuit comprises a power semiconductor transistor.

12. The circuit package of claim 1 ,
wherein the at least one first contact pad comprises a first source/drain contact pad and a gate contact pad electrically isolated from the first source/drain contact pad; and
wherein the at least one second contact pad comprises a second source/drain contact pad.

13. The circuit package of claim 1 ,
wherein the first metal layer structure comprises
a first metal layer structure first portion electrically contacted to the first source/drain contact pad on the first side of the electronic circuit;
a first metal layer structure second portion electrically contacted to the gate contact pad on the first side of the electronic circuit; and
a first metal layer structure third portion electrically contacted to the metal block, wherein at least one of the first metal layer structure first portion, second portion and third portion, is electrically isolated from each other.

14. The circuit package of claim 1 ,
wherein the encapsulation material comprises at least one electrically insulating material from the group of electrically insulating materials, the group consisting of: an epoxy, a polymer, a laminate, a plastic, a thermoset, a thermoplastic, polyimide, and combinations thereof.

15. The circuit package of claim 1 ,
wherein the encapsulation material is formed on one or more lateral sides of the electronic circuit wherein the one or more lateral sides of the electronic circuit are arranged between the first side and the second side of the electronic circuit.

16. The circuit package of claim 1 ,
wherein the one or more metal blocks are externally exposed on one or more sides of the circuit package.

17. The circuit package of claim 1 , wherein a difference between the first temperature and the second temperature is determined at least by a melting temperature of first metallic element and a melting temperature of the second metallic element.

18. An electronic circuit package, comprising:
an encapsulation material configured to hold one or more metal blocks next to a semiconductor chip, wherein the encapsulation material is formed between the semiconductor chip and the metal block;
a first metal layer structure configured to electrically contact at least one first contact pad on a first side of the semiconductor chip;
a second metal layer structure configured to electrically contact at least one second contact pad on a second side of the semiconductor chip, wherein the second side is opposite to the first side;
a joining material between the at least one first contact pad and the first metal layer structure; and
an electrically conductive medium comprising a first electrically conductive medium electrically contacting the metal block to the first metal layer structure and a second electrically conductive medium electrically contacting the metal block to the second metal layer structure;
wherein the first metal layer structure and the second metal layer structure comprise a metallic element;
wherein the first electrically conductive medium comprises a first intermetallic phase material comprising a first metallic element that is a different element than the metallic element and the secon

Assignees

• Hosseini Khalil
• Mahler Joachim
• Fuergut Edward
• Infineon Technologies Ag

Inventors

• Hosseini Khalil
• Mahler Joachim
• Fuergut Edward

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07332

  Compression bonding, e.g. thermocompression bonding · CPC title