Electronic substrates having embedded dielectric magnetic material to form inductors

Patent metadata

Field	Value
Publication number	US-11189409-B2
Application number	US-201715856547-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An inductor may be fabricated comprising a magnetic material layer and an electrically conductive via or trace extending through the magnetic material layer, wherein the magnetic material layer comprises dielectric magnetic filler particles within a carrier material. Further embodiments may include incorporating the inductor of the present description into an electronic substrate and may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

First claim

What is claimed is:

1. An inductor comprising a magnetic material layer and an electrically conductive via extending through the magnetic material layer, wherein the magnetic material layer comprises a layered stack comprising a center layer comprising iron/cobalt/nickel alloy dielectric magnetic filler particles in a carrier material between a pair of exterior layers comprising nickel/iron alloy dielectric magnetic filler particles in a carrier material.

2. The inductor of claim 1 , wherein the iron/cobalt/nickel alloy dielectric magnetic filler particles and the nickel/iron alloy dielectric magnetic filler particles have a resistivity of greater than about 5.5e-7 ohm meters.

3. The inductor of claim 1 , wherein the iron/cobalt/nickel alloy filler particles comprise (Fe 0.7 Co 0.3 ) 0.95 Ni 0.05 .

4. The inductor of claim 1 , wherein the nickel iron alloy filler particles comprise Ni 0.81 Fe 0.19 .

5. The inductor of claim 1 , wherein at least one of the carrier material of the center layer and the carrier material of one of the pair of exterior layers comprises a polymer resin.

6. An electronic system, comprising:
a board; and
an electronic package attached to the board, wherein the electronic package comprises:
an electronic substrate having at least one dielectric layer;
an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer and an electrically conductive via extending through the magnetic material layer, wherein the magnetic material layer comprises a layered stack comprising a center layer comprising iron/cobalt/nickel alloy dielectric magnetic filler particles in a carrier material between a pair of exterior layers comprising nickel/iron alloy dielectric magnetic filler particles in a carrier material.

7. The electronic system of claim 6 , wherein the iron/cobalt/nickel alloy dielectric magnetic filler particles and the nickel/iron alloy dielectric magnetic filler particles have a resistivity of greater than about 5.5e-7 ohm meters.

8. The electronic system of claim 6 , wherein the iron/cobalt/nickel alloy filler particles comprise (Fe 0.7 Co 0.3 ) 0.95 Ni 0.05 .

9. The electronic system of claim 6 , wherein the nickel iron alloy filler particles comprise Ni 0.81 Fe 0.19 .

10. The electronic system of claim 6 , wherein at least one of the carrier material of the center layer and the carrier material of the pair of exterior layers comprises a polymer resin.

11. The electronic system of claim 6 , wherein the electronic substrate includes a substrate core.

12. A method of fabricating an electronic structure, comprising:
forming at least one dielectric layer;
forming at least one via through the at least one dielectric layer;
forming a magnetic material layer within the at least one via, wherein the magnetic material layer comprises a layered stack comprising a center layer comprising iron/cobalt/nickel alloy dielectric magnetic filler particles in a carrier material between a pair of exterior layers comprising nickel/iron alloy dielectric magnetic filler particles in a carrier material; and
forming an electrically conductive via extending through the magnetic material layer.

13. The method of claim 12 , wherein the iron/cobalt/nickel alloy dielectric magnetic filler particles and the nickel/iron alloy dielectric magnetic filler particles have a resistivity of greater than about 5.5e-7 ohm meters.

14. The method of claim 12 , wherein the iron/cobalt/nickel alloy filler particles comprise (Fe 0.7 Co 0.3 ) 0.95 Ni 0.05 .

15. The method of claim 12 , wherein the nickel iron alloy filler particles comprise Ni 0.81 Fe 0.19 .

16. The method of claim 12 , wherein at least one of the carrier material of the center layer and the carrier material of one of the pair of exterior layers comprises a polymer resin.

Assignees

• Intel Corp

Inventors

• Brown Andrew J
• Chatterjee Prithwish
• Link Lauren A
• Vadlamani Sai

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/07236

  Soldering or alloying · CPC title